ST7MDT2-EPB2/US STMicroelectronics, ST7MDT2-EPB2/US Datasheet - Page 65
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ST7MDT2-EPB2/US
Manufacturer Part Number
ST7MDT2-EPB2/US
Description
BOARD PROGRAMMING SGL POS ST7
Manufacturer
STMicroelectronics
Type
MCUr
Specifications of ST7MDT2-EPB2/US
Contents
Programmer Board
For Use With/related Products
ST72311, ST72124, ST72314, ST72334
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 65 of 153
- Download datasheet (3Mb)
16-BIT TIMER (Cont’d)
14.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The Pulse Width Modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functions cannot be used
when the PWM mode is activated.
Procedure
To use Pulse Width Modulation mode:
1. Load the OC2R register with the value corre-
2. Load the OC1R register with the value corre-
3. Select the following in the CR1 register:
4. Select the following in the CR2 register:
If OLVL1=1 and OLVL2=0, the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
sponding to the period of the signal using the
formula in the opposite column.
sponding to the period of the pulse if OLVL1=0
and OLVL2=1, using the formula in the oppo-
site column.
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
– Set OC1E bit: the OCMP1 pin is then dedicat-
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see
plied to the OCMP1 pin after a successful
comparison with OC1R register.
plied to the OCMP1 pin after a successful
comparison with OC2R register.
ed to the output compare 1 function.
Clock Control
Counter
= OC1R
Counter
= OC2R
When
When
Bits).
Pulse Width Modulation cycle
OCMP1 = OLVL2
OCMP1 = OLVL1
Counter is reset
ICF1 bit is set
to FFFCh
Table 14
The OC
ing application can be calculated using the follow-
ing formula:
Where:
t
f
PRESC
If the timer clock is an external clock the formula is:
Where:
t
f
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See
Notes:
1. After a write instruction to the OC i HR register,
2. The OCF1 and OCF2 bits cannot be set by
3. The ICF1 bit is set by hardware when the coun-
4. In PWM mode the ICAP1 pin can not be used
5. When the Pulse Width Modulation (PWM) and
CPU
EXT
the output compare function is inhibited until the
OC i LR register is also written.
hardware in PWM mode, therefore the Output
Compare interrupt is inhibited.
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
to perform input capture because it is discon-
nected from the timer. The ICAP2 pin can be
used to perform input capture (ICF2 can be set
and IC2R can be loaded) but the user must
take care that the counter is reset after each
period and ICF1 can also generate an interrupt
if ICIE is set.
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
ST72334J/N, ST72314J/N, ST72124J
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 depend-
i
R register value required for a specific tim-
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
OC i R Value =
ing on CC[1:0] bits, see
Control
OC i R =
Bits)
t
*
f
EXT
PRESC
t
*
f
CPU
-5
Figure
Table 14 Clock
- 5
41)
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