C8051F226-TB Silicon Laboratories Inc, C8051F226-TB Datasheet - Page 25

• Manufacturer Part Number: C8051F226-TB
• Description: BOARD PROTOTYPING W/C8051F226
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226-TB

• Contents: Board
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F226
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.
P0.2/INT0
MONEN
P0.1/RX
P0.0/TX
XTAL1
XTAL2
Name
VREF
CP0+
CP1+
CP0-
CP1-
GND
TMS
TDO
TCK
RST
CP0
CP1
V
TDI
Pinout and Package Definitions
DD
48-Pin 32-Pin
5,6,8,
13,32
11,31
‘F206,
F220,
226,
230,
236
12
25
26
28
27
10
14
48
47
40
39
38
9
7
4
3
2
1
‘F221,
231
17
18
20
19
10
32
31
28
27
26
8
9
6
7
5
4
3
2
1
D Out JTAG Test Data Output. Data is shifted out on TDO on the falling
A Out
D Out
D Out
D I/O
A I/O
D I/O
D I/O
D I/O
Type
D In
D In
D In
D In
A In
A In
A In
A In
A In
A In
A In
A In
Table 4.1. Pin Definitions
connected (NC), but it is recommended that they be connected to
tor. Is driven low when V
voltage reference for the ADC. Otherwise, V
XTAL2. If overdriven by an external CMOS clock, this becomes
Chip Reset. Open-drain output of internal Voltage Supply moni-
Voltage Reference. When configured as an input, this pin is the
Crystal Input. This pin is the return for the internal oscillator cir-
Ground. ( Note: Pins 5,6, and 8 on the 48-pin package are not
Monitor Enable (on 48 pin package ONLY). Enables reset volt-
Port0 Bit0. (See the Port I/O Sub-System section for complete
Port0 Bit1. (See the Port I/O Sub-System section for complete
Port0 Bit2. (See the Port I/O Sub-System section for complete
JTAG Test Data Input with internal pull-up. TDI is latched on a
‘1’is written to PORSF. An external source can force a system
cuit for a crystal or ceramic resonator. For a precision internal
Crystal Output. This pin is the excitation driver for a crystal or
clock, connect a crystal or ceramic resonator from XTAL1 to
ence. NOTE: this pin is Not Connected (NC) on ‘F230/1/6.
age monitor function when pulled high (logic “1”).
Rev. 1.6
edge of TCK. TDO output is a tri-state driver.
JTAG Test-Mode Select with internal pull-up.
JTAG Test Clock with internal pull-up.
Comparator 0 Non-Inverting Input.
Comparator 1 Non-Inverting Input.
Comparator 0 Inverting Input.
Comparator 1 Inverting Input.
reset by driving this pin low.
Digital Voltage Supply.
Comparator 0 Output
Comparator 1 Output
rising edge of TCK.
ceramic resonator.
the system clock.
DD
Description
description).
description).
description).
ground.)
is < 2.7V and MONEN=1, or when a
C8051F2xx
DD
will be the refer-
25