C8051F226-TB Silicon Laboratories Inc, C8051F226-TB Datasheet - Page 84
C8051F226-TB
Manufacturer Part Number
C8051F226-TB
Description
BOARD PROTOTYPING W/C8051F226
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F226-TB
Contents
Board
Processor To Be Evaluated
C8051F22x and C8051F23x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F226
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F2xx
down all digital peripherals. Each analog peripheral must be shut down individually prior to entering Stop
Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD
timeout of 100 sec.
84
Bit7:
Bits6–2: GF4–GF0: General Purpose Flags 4–0.
Bit1:
Bit0:
SMOD
R/W
Bit7
SMOD: Serial Port Baud Rate Doubler Enable.
0: Serial Port baud rate is that defined by Serial Port Mode in SCON.
1: Serial Port baud rate is double that defined by Serial Port Mode in SCON.
These are general purpose flags for use under software control.
STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: Goes into power down mode. (Turns off internal oscillator).
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
GF4
R/W
Bit6
SFR Definition 9.14. PCON: Power Control Register
GF3
R/W
Bit5
GF2
R/W
Bit4
Rev. 1.6
GF1
R/W
Bit3
GF0
R/W
Bit2
STOP
R/W
Bit1
IDLE
R/W
Bit0
SFR Address:
Reset Value
00000000
0x87
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