C8051F005-TB Silicon Laboratories Inc, C8051F005-TB Datasheet - Page 105

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C8051F005-TB

Manufacturer Part Number
C8051F005-TB
Description
BOARD PROTOTYPING W/C8051F005
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F005-TB

Contents
Board
Data Bus Width
8 bit
Silicon Manufacturer
Silicon Laboratories
Core Architecture
8051
Silicon Family Name
C8051F00x
Kit Contents
Board
Features
JTAG Connector, Debug Adapter Interface, Analog I/O Configuration
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F005
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
In the Priority Decode Table, a dot () is used to show the external Port I/O pin (column) to which each signal (row)
can be assigned by the user application code via programming registers XBR2, XBR1, and XBR0.
105
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SDA
SCL
SCK
MISO
MOSI
NSS
TX
RX
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
CP0
CP1
T0
/INT0
T1
/INT1
T2
T2EX
/SYSCLK
CNVSTR
PIN I/O 0
             
              
               
                
                 
                  
                   
                    
                     
                      
                       
1
2
3
P0
4
Table 15.1. Crossbar Priority Decode
5
6
7
0
1
Rev. 1.7
2
3
P1
4
5
6
7
0
1
2
3
P2
4
5
6
7

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