C8051F350-TB Silicon Laboratories Inc, C8051F350-TB Datasheet - Page 5
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C8051F350-TB
Manufacturer Part Number
C8051F350-TB
Description
PROTOTYPINGBOARDWITH C8051F350
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F350-TB
Contents
Board
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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18. Port Input/Output.................................................................................................. 137
19. SMBus ................................................................................................................... 151
20. UART0.................................................................................................................... 171
21. Serial Peripheral Interface (SPI0) ........................................................................ 181
17.3.Clock Multiplier ............................................................................................... 135
17.4.System Clock Selection.................................................................................. 136
18.1.Priority Crossbar Decoder .............................................................................. 139
18.2.Port I/O Initialization ....................................................................................... 141
18.3.General Purpose Port I/O ............................................................................... 144
19.1.Supporting Documents ................................................................................... 152
19.2.SMBus Configuration...................................................................................... 152
19.3.SMBus Operation ........................................................................................... 152
19.4.Using the SMBus............................................................................................ 155
19.5.SMBus Transfer Modes.................................................................................. 163
19.6.SMBus Status Decoding................................................................................. 167
20.1.Enhanced Baud Rate Generation................................................................... 172
20.2.Operational Modes ......................................................................................... 173
20.3.Multiprocessor Communications .................................................................... 174
21.1.Signal Descriptions......................................................................................... 182
21.2.SPI0 Master Mode Operation ......................................................................... 183
21.3.SPI0 Slave Mode Operation ........................................................................... 185
21.4.SPI0 Interrupt Sources ................................................................................... 185
21.5.Serial Clock Timing......................................................................................... 186
21.6.SPI Special Function Registers ...................................................................... 186
17.2.2.External Crystal Example....................................................................... 131
17.2.3.External RC Example............................................................................. 133
17.2.4.External Capacitor Example................................................................... 133
19.3.1.Arbitration............................................................................................... 153
19.3.2.Clock Low Extension.............................................................................. 154
19.3.3.SCL Low Timeout................................................................................... 154
19.3.4.SCL High (SMBus Free) Timeout .......................................................... 154
19.4.1.SMBus Configuration Register............................................................... 156
19.4.2.SMB0CN Control Register ..................................................................... 159
19.4.3.Data Register ......................................................................................... 162
19.5.1.Master Transmitter Mode ....................................................................... 163
19.5.2.Master Receiver Mode ........................................................................... 164
19.5.3.Slave Receiver Mode ............................................................................. 165
19.5.4.Slave Transmitter Mode ......................................................................... 166
20.2.1.8-Bit UART ............................................................................................. 173
20.2.2.9-Bit UART ............................................................................................. 174
21.1.1.Master Out, Slave In (MOSI).................................................................. 182
21.1.2.Master In, Slave Out (MISO).................................................................. 182
21.1.3.Serial Clock (SCK) ................................................................................. 182
21.1.4.Slave Select (NSS) ................................................................................ 182
Rev. 1.1
C8051F350/1/2/3
5
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