COP8-REF-FL1 National Semiconductor, COP8-REF-FL1 Datasheet - Page 31

• Manufacturer Part Number: COP8-REF-FL1
• Description: KIT REF DESIGN FOR COP8SDR9
• Manufacturer: National Semiconductor
• Series: COP8™r
• Type: MCUr

Specifications of COP8-REF-FL1

• Design Resources: COP8 Flash Ref Design Flyer
• Contents: PCB, Control Interface, Documentation and 9V Battery
• For Use With/related Products: COP8SDR9
• Lead Free Status / RoHS Status: Not applicable / Not applicable

7.0 Power Saving Features
lator has a sufficiently large amplitude to meet the Schmitt
trigger specifications. This Schmitt trigger is not part of the
oscillator closed loop. The start-up time-out from the IDLE
timer enables the clock signals to be routed to the rest of the
chip.
The device has two options associated with the HALT mode.
The first option enables the HALT mode feature, while the
second option disables the HALT mode selected through bit
1 of the Option register. With the HALT mode enable option,
the device will enter and exit the HALT mode as described
above. With the HALT disable option, the device cannot be
placed in the HALT mode (writing a “1” to the HALT flag will
have no effect, the HALT flag will remain “0”).
7.2 IDLE MODE
The device is placed in the IDLE mode by writing a ’1’ to the
IDLE flag (G6 data bit). In this mode, all activities, except the
associated on-board oscillator circuitry, the WATCHDOG
logic, the clock monitor and the IDLE Timer T0, are stopped.
The power supply requirements of the microcontroller in this
mode of operation are significantly lower than the normal
power requirement of the microcontroller.
As with the HALT mode, the device can be returned to
normal operation with a reset, or with a Multi-Input Wake-up
from the L Port. Alternatively, the microcontroller may also be
awakened from the IDLE mode after a selectable amount of
time up to 65,536 Idle Timer Clocks or 32.768 milliseconds
with an internal clock frequency of 20 MHz.
The IDLE timer period is selectable from one of five values,
4k, 8k, 16k, 32k or 64k Idle Timer Clocks. Selection of this
value is made through the ITMR register. When the selected
bit of the IDLE Timer toggles, the T0PND bit of the ICNTRL
Register is set.
The user has the option of being interrupted when the
T0PND bit is set. The interrupt can be enabled or disabled
via the T0EN control bit. Setting the T0EN flag enables the
interrupt and vice versa.
FIGURE 17. Wake-up from HALT
(Continued)
31
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
It is recommended that the user not halt the device by merely
stopping the clock in external oscillator mode. If this method
is used, there is a possibility of greater than specified HALT
current.
If the user wishes to stop an external clock, it is recom-
mended that the CPU be halted by setting the Halt flag first
and the clock be stopped only after the CPU has halted.
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the ’Enter Idle
Mode’ instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the ’Enter IDLE Mode’ instruction.
Note: It is necessary to program two NOP instructions following both the set
For more information on the IDLE Timer and its associated
interrupt, see the description in Section 6.1 TIMER T0 (IDLE
TIMER) .
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
20026470
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