COP8-REF-FL1 National Semiconductor, COP8-REF-FL1 Datasheet - Page 8

• Manufacturer Part Number: COP8-REF-FL1
• Description: KIT REF DESIGN FOR COP8SDR9
• Manufacturer: National Semiconductor
• Series: COP8™r
• Type: MCUr

Specifications of COP8-REF-FL1

• Design Resources: COP8 Flash Ref Design Flyer
• Contents: PCB, Control Interface, Documentation and 9V Battery
• For Use With/related Products: COP8SDR9
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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Input Capacitance
Voltage on G6 to Force Execution from Boot
ROM(Note 8)
G6 Rise Time to Force Execution from Boot ROM
Input Current on G6 when Input
Flash Memory Data Retention
Flash Memory Number of Erase/Write Cycles
2.0 Electrical Characteristics
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Instruction Cycle Time (t
Flash Memory Page Erase Time
Flash Memory Mass Erase Time
Frequency of MICROWIRE/PLUS in
Slave Mode
MICROWIRE/PLUS Setup Time (t
MICROWIRE/PLUS Hold Time (t
MICROWIRE/PLUS Output Propagation
Delay (t
Input Pulse Width
Output Pulse Width
Reset Pulse Width
t
Note 2: Maximum rate of voltage change must be
Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 4: The HALT mode will stop CKI from oscillating. Measurement of I
H and L programmed as low outputs and not driving a load; all inputs tied to V
mode entered via setting bit 7 of the G Port data register.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
biased at voltages
be limited to
Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 t
Note 7: Absolute Maximum Ratings should not be exceeded.
Note 8: V
C
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Crystal/Resonator
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Timer 2 Input High Time (Note 6)
Timer 2 Input Low Time (Note 6)
Timer 2 Output High Time
Timer 2 Output Low Time
= instruction cycle time.
UPD
cc
must be valid and stable before G6 is raised to a high voltage.
<
)
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
>
Parameter
V
Parameter
CC
(the pins do not have source current when biased at a voltage below V
C
TABLE 1. DC Electrical Characteristics (−40˚C
)
>
UWH
V
UWS
CC
AC Electrical Characteristics (−40˚C
)
)
<
0.5 V/ms.
4.5V
2.7V
See Table 14 , Typical
Flash Memory
Endurance
(Continued)
G6 rise time must be slower
than 100 ns
V
25˚C
See Table 14 , Typical Flash
Memory Endurance
IN
Conditions
V
V
= 11V, V
CC
CC
DD
<
Conditions
HALT is done with device neither sourcing nor sinking current; with A. B, G0, G2–G5,
5.5V
4.5V
CC
8
CC
; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT
= 5.5V
CC
T
). These two pins will not latch up. The voltage at the pins must
T
A
A
Min
150
150
0.5
1.5
20
20
1
1
1
1
1
1
1
+85˚C) (Continued)
+85˚C)
>
2 x V
V
Min
100
CC
CC
and the pins will have sink current to V
Typ
1
8
Typ
500
100
10
C
5
.
Max
150
DC
DC
2
V
CC
Max
7
+ 7
MCLK or t
MCLK or t
Units
MHz
ms
ms
CC
µs
µs
ns
ns
ns
ns
ns
t
t
t
t
t
C
C
C
C
C
cycles
when
Units
yrs
pF
nS
µA
CC
V
C
C