MC56F8323EVME Freescale Semiconductor, MC56F8323EVME Datasheet - Page 90

• Manufacturer Part Number: MC56F8323EVME
• Description: BOARD EVALUATION MC56F8323
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8323EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8322 and MC56F8323
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8322, MC56F8323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5.6.3
This bit controls the pull-up resistors on the IRQA pin.
6.5.6.4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.5
This bit controls the pull-up resistors on the TRST, TMS, and TDI pins.
6.5.6.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are
for test purposes only, and are subject to significant unspecified latencies at high frequencies.
The upper four bits of the GPIOB register can function as GPIO, Quad Decoder #0 signals, or as additional
clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are
programmed to operate as peripheral outputs, then the choice between Quad Decoder #0 and additional
clock outputs is made here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4]
to be programmed as Quad Decoder #0. This can be changed by altering PHASE0 through INDEX shown
in
The CLKOUT pin is not bonded out in the device. Instead, it is offered only as a pad for die-level testing.
6.5.7.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7.2
6.5.7.3
90
Figure
•
•
•
•
Base + $A
0 = Peripheral output function of GPIOB[7] is defined to be PHASEA0
1 = Peripheral output function of GPIOB[7] is defined to be the oscillator clock (MSTR_OSC, see
Figure
0 = Peripheral output function of GPIOB[6] is defined to be PHASEB0
1 = Peripheral output function of GPIOB[6] is defined to be SYS_CLK2
RESET
Write
Read
6-9.
CLKO Select Register (SIM_CLKOSR)
IRQ—Bit 10
Reserved—Bits 9–4
JTAG—Bit 3
Reserved—Bits 2–0
Reserved—Bits 15–10
PHASEA0 (PHSA)—Bit 9
PHASEB0 (PHSB)—Bit 8
3-4)
15
0
0
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
14
0
0
13
0
0
12
0
0
56F8323 Technical Data, Rev. 17
11
0
0
10
0
0
PHSA PHSB INDEX HOME
9
0
8
0
7
0
6
0
CLK
DIS
5
1
4
0
3
0
Freescale Semiconductor
CLKOSEL
2
0
1
0
Preliminary
0
0