HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 27
![EVALUATION PLATFORM VIRTEX-5](/photos/24/12/241250/4651631_sml.jpg)
HW-V5-ML506-UNI-G
Manufacturer Part Number
HW-V5-ML506-UNI-G
Description
EVALUATION PLATFORM VIRTEX-5
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Type
DSPr
Datasheet
1.HW-V5-ML507-UNI-G.pdf
(60 pages)
Specifications of HW-V5-ML506-UNI-G
Contents
Evaluation Platform, DVI Adapter and CompactFlash Card
Silicon Manufacturer
Xilinx
Features
JTAG Programming Interface, Platform Flash, External Clocking
Kit Contents
Board, Cable, PSU, CD, Docs
Silicon Family Name
Virtex-5
Silicon Core Number
XC5VSX50TFFG1136
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
XC5VSX50TFFG1136
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
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ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
12. RS-232 Serial Port
13. 16-Character x 2-Line LCD
14. IIC Bus with 8-Kb EEPROM
15. DVI Connector
R
The ML50x board contains one male DB-9 RS-232 serial port, allowing the FPGA to
communicate serial data with another device. The serial port is wired as a host (DCE)
device. Therefore, a null modem cable is normally required to connect the board to the
serial port on a computer. The serial port is designed to operate up to 115200 Bd. An
interface chip is used to shift the voltage level between FPGA and RS-232 signals.
Note:
RS-232 signals, including hardware flow-control signals, are not used. Flow control should be
disabled when communicating with a computer.
A secondary serial interface is available by using header J61 to support debug of the USB
controller chip. Header J61 brings out RS-232 voltage level signals for ground, TX data, and
RX data.
The ML50x board has a 16-character x 2-line LCD (Tianma TM162VBA6) on the board to
display text information. Potentiometer R87 adjusts the contrast of the LCD. The data
interface to the LCD is connected to the FPGA to support 4-bit mode only. The CPLD is
used to shift the voltage level between the FPGA and the LCD. The LCD module has a
connector that allows the LCD to be removed from the board to access to the components
below it.
An IIC EEPROM (STMicroelectronics M24C08) is provided on the board to store non-
volatile data such as an Ethernet MAC address. The EEPROM write protect is disabled on
the board. IIC bus pull-up resistors are provided on the board.
The IIC bus is extended to the expansion connector so that the user can add additional IIC
devices and share the IIC controller in the FPGA. If the expansion IIC bus is to be utilized,
the user must have additional IIC pull-up resistors present on the expansion card.
Bidirectional level shifting transistors allow the expansion card to utilize 2.5V to 5V
signaling on IIC.
A DVI connector (P7) is present on the board to support an external video monitor. The
DVI circuitry utilizes a Chrontel CH7301C capable of 1600 X 1200 resolution with 24-bit
color. The video interface chip drives both the digital and analog signals to the DVI
connector. A DVI monitor can be connected to the board directly. A VGA monitor can also
be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel
CH7301C is controlled by way of the video IIC bus.
Caution!
The FPGA is connected only to the TX and RX data pins on the serial port. Therefore, other
Care should be taken not to scratch or damage the surface of the LCD window.
www.xilinx.com
Detailed Description
27