HW-V5-ML510-G Xilinx Inc, HW-V5-ML510-G Datasheet
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ML510 ML510 Embedded Embedded Development Platform Development User Guide [optional] User Guide UG356 (v1.1 ) December 11, 2008 [optional] UG356 (v1.1 ) December 11, 2008 R ...
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
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Table of Contents Preface: About This Guide Additional Documentation Additional Support Resources Typographical Conventions Online Document . . . . . . . . . . . . . . . . . . . . . . . . ...
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Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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R About This Guide This manual accompanies the ML510 series of Embedded Development Platforms and contains information about the ML510 hardware and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “ML510 Embedded Development Platform” embedded ...
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Preface: About This Guide • XtremeDSP Design Considerations This guide describes the XtremeDSP™ slice and includes reference designs for using the DSP48E. • Virtex-5 FPGA Configuration Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream ...
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R Convention Red text Blue, underlined text ML510 Embedded Development Platform UG356 (v1.1 ) December 11, 2008 Typographical Conventions Meaning or Use Cross-reference link to a See location in another document Sheet Go to Hyperlink to a website (URL) for ...
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Preface: About This Guide 8 www.xilinx.com ML510 Embedded Development Platform UG356 (v1.1 ) December 11, 2008 R ...
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R ML510 Embedded Development Platform Overview The ML510 series of Embedded Development Platforms offer designers a versatile Virtex®-5 FXT platform for rapid prototyping and system verification. In addition to the more than 130,000 logic cells, over 10,700 kb of block ...
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Chapter 1: ML510 Embedded Development Platform Additional Information Additional information and support material is located at: • http://www.xilinx.com/ml510 This information includes: • Current version of this user guide in PDF format • Example design files for demonstration of Virtex-5 FPGA ...
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R • JTAG and trace debug ports • High-speed I/O through RocketIO GTX transceivers • Encryption battery • Fan controller • Onboard power regulators for all necessary voltages • IIC/SMBus interface* ♦ LTC1694 SMBus accelerator ♦ RTC8566 Real Time Clock ...
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Chapter 1: ML510 Embedded Development Platform • ISE: www.xilinx.com/ise • Answer Browser: • Intellectual Property: Detailed Description The ML510, shown in guide. X-Ref Target - Figure 1-2 System ACE Configuration DIP Switch, SW3 GPIO Header, J5 Prog Pushbutton, SW4 System ...
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R Virtex-5 FPGA A Xilinx Virtex-5 FPGA, XC5VFX130T-2FFG1738C, is installed on the Embedded Development Platform (the board). Configuration ML510 platforms support configuration in JTAG mode only. Configuration can be accomplished by using a Xilinx download cable (such as Parallel Cable ...
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Chapter 1: ML510 Embedded Development Platform Table 1-1: I/O Voltage Rail of FPGA Banks (Cont’d) FPGA Bank I/O Voltage Rail 25 26 Clock Generation ML510 boards are equipped with two crystal oscillator sockets (X6 and X10) each wired for standard ...
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R Figure 1-3 X-Ref Target - Figure 1-3 OSC USER_CLK Socket OSC USER_CLK2 Open Socket OSC SysAce_CLK Soldered SMA CLK ICS85104 ICS843011 (LVPECL) 1:4 100MHz 25MHz SMA_MGT_CLK ML510 Embedded Development Platform UG356 (v1.1 ) December 11, 2008 is an example ...
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Chapter 1: ML510 Embedded Development Platform Table 1-2 shows the ML510 clock connections. Table 1-2: Clock Connections Schematic Net Name USER_CLKSYS USER_CLK2 USER_SMA_CLK_N USER_SMA_CLK_P PM_CLK_TOP PM_CLK_BOT LVDS_CLKEXT_P_C LVDS_CLKEXT_N_C SGMIICLK_QO_P SGMIICLK_QO_N GTP_SMA_CLK_P GTP_SMA_CLK_N SATACLK_QO_P SATACLK_QO_N Notes: 1. See “High-Speed I/O,” page ...
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R The board’s DDR2 memory interfaces are designed to the requirements defined by the Xilinx Memory Interface Generator (MIG) User Guide MIG documentation requires that designers follow the MIG pinout and layout guidelines. The MIG tool generates and ensures that ...
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Chapter 1: ML510 Embedded Development Platform Table 1-3, page 18 memories. Note that the DDR2_DQ signal names do not correlate because the FPGA uses IBM notation, big endian, while the DDR2 DIMM uses Intel notation, little endian. Table 1-3: Connections ...
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R Table 1-3: Connections from FPGA to DDR2 DIMM0 Interface (P48) (Cont’d) Schematic Net Name DIMM0_DDR2_DQM4 DIMM0_DDR2_DQM3 DIMM0_DDR2_DQM2 DIMM0_DDR2_DQM1 DIMM0_DDR2_DQM0 DIMM0_DDR2_DQ63 DIMM0_DDR2_DQ62 DIMM0_DDR2_DQ61 DIMM0_DDR2_DQ60 DIMM0_DDR2_DQ59 DIMM0_DDR2_DQ58 DIMM0_DDR2_DQ57 DIMM0_DDR2_DQ56 DIMM0_DDR2_DQ55 DIMM0_DDR2_DQ54 DIMM0_DDR2_DQ53 DIMM0_DDR2_DQ52 DIMM0_DDR2_DQ51 DIMM0_DDR2_DQ50 DIMM0_DDR2_DQ49 DIMM0_DDR2_DQ48 DIMM0_DDR2_DQ47 DIMM0_DDR2_DQ46 DIMM0_DDR2_DQ45 DIMM0_DDR2_DQ44 ...
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Chapter 1: ML510 Embedded Development Platform Table 1-3: Connections from FPGA to DDR2 DIMM0 Interface (P48) (Cont’d) Schematic Net Name DIMM0_DDR2_DQ35 DIMM0_DDR2_DQ34 DIMM0_DDR2_DQ33 DIMM0_DDR2_DQ32 DIMM0_DDR2_DQ31 DIMM0_DDR2_DQ30 DIMM0_DDR2_DQ29 DIMM0_DDR2_DQ28 DIMM0_DDR2_DQ27 DIMM0_DDR2_DQ26 DIMM0_DDR2_DQ25 DIMM0_DDR2_DQ24 DIMM0_DDR2_DQ23 DIMM0_DDR2_DQ22 DIMM0_DDR2_DQ21 DIMM0_DDR2_DQ20 DIMM0_DDR2_DQ19 DIMM0_DDR2_DQ18 DIMM0_DDR2_DQ17 DIMM0_DDR2_DQ16 ...
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R Table 1-3: Connections from FPGA to DDR2 DIMM0 Interface (P48) (Cont’d) Schematic Net Name DIMM0_DDR2_DQ2 DIMM0_DDR2_DQ1 DIMM0_DDR2_DQ0 DIMM0_DDR2_CKE1 DIMM0_DDR2_CKE0 DIMM0_DDR2_CB7 DIMM0_DDR2_CB6 DIMM0_DDR2_CB5 DIMM0_DDR2_CB4 DIMM0_DDR2_CB3 DIMM0_DDR2_CB2 DIMM0_DDR2_CB1 DIMM0_DDR2_CB0 DIMM0_DDR2_CAS_B DIMM0_DDR2_BA2 DIMM0_DDR2_BA1 DIMM0_DDR2_BA0 DIMM0_DDR2_A13 DIMM0_DDR2_A12 DIMM0_DDR2_A11 DIMM0_DDR2_A10 DIMM0_DDR2_A9 DIMM0_DDR2_A8 DIMM0_DDR2_A7 DIMM0_DDR2_A6 ...
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Chapter 1: ML510 Embedded Development Platform Table 1-4: Connections from FPGA to DDR2 DIMM1 Interface (P9) UCF Signal Name DIMM1_DDR2_WE_B DIMM1_DDR2_S1_B DIMM1_DDR2_S0_B DIMM1_DDR2_RAS_B DIMM1_DDR2_CAS_B DIMM1_DDR2_PLL_CLKIN_P DIMM1_DDR2_PLL_CLKIN_N DIMM1_DDR2_ODT1 DIMM1_DDR2_ODT0 DIMM1_DDR2_DQS8_P DIMM1_DDR2_DQS8_N DIMM1_DDR2_DQS7_P DIMM1_DDR2_DQS7_N DIMM1_DDR2_DQS6_P DIMM1_DDR2_DQS6_N DIMM1_DDR2_DQS5_P DIMM1_DDR2_DQS5_N DIMM1_DDR2_DQS4_P DIMM1_DDR2_DQS4_N DIMM1_DDR2_DQS3_P DIMM1_DDR2_DQS3_N ...
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R Table 1-4: Connections from FPGA to DDR2 DIMM1 Interface (P9) (Cont’d) UCF Signal Name DIMM1_DDR2_DQM3 DIMM1_DDR2_DQM2 DIMM1_DDR2_DQM1 DIMM1_DDR2_DQM0 DIMM1_DDR2_DQ63 DIMM1_DDR2_DQ62 DIMM1_DDR2_DQ61 DIMM1_DDR2_DQ60 DIMM1_DDR2_DQ59 DIMM1_DDR2_DQ58 DIMM1_DDR2_DQ57 DIMM1_DDR2_DQ56 DIMM1_DDR2_DQ55 DIMM1_DDR2_DQ54 DIMM1_DDR2_DQ53 DIMM1_DDR2_DQ52 DIMM1_DDR2_DQ51 DIMM1_DDR2_DQ50 DIMM1_DDR2_DQ49 DIMM1_DDR2_DQ48 DIMM1_DDR2_DQ47 DIMM1_DDR2_DQ46 DIMM1_DDR2_DQ45 DIMM1_DDR2_DQ44 DIMM1_DDR2_DQ43 ...
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Chapter 1: ML510 Embedded Development Platform Table 1-4: Connections from FPGA to DDR2 DIMM1 Interface (P9) (Cont’d) UCF Signal Name DIMM1_DDR2_DQ34 DIMM1_DDR2_DQ33 DIMM1_DDR2_DQ32 DIMM1_DDR2_DQ31 DIMM1_DDR2_DQ30 DIMM1_DDR2_DQ29 DIMM1_DDR2_DQ28 DIMM1_DDR2_DQ27 DIMM1_DDR2_DQ26 DIMM1_DDR2_DQ25 DIMM1_DDR2_DQ24 DIMM1_DDR2_DQ23 DIMM1_DDR2_DQ22 DIMM1_DDR2_DQ21 DIMM1_DDR2_DQ20 DIMM1_DDR2_DQ19 DIMM1_DDR2_DQ18 DIMM1_DDR2_DQ17 DIMM1_DDR2_DQ16 DIMM1_DDR2_DQ15 ...
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R Table 1-4: Connections from FPGA to DDR2 DIMM1 Interface (P9) (Cont’d) UCF Signal Name DIMM1_DDR2_DQ1 DIMM1_DDR2_DQ0 DIMM1_DDR2_CKE1 DIMM1_DDR2_CKE0 DIMM1_DDR2_CB7 DIMM1_DDR2_CB6 DIMM1_DDR2_CB5 DIMM1_DDR2_CB4 DIMM1_DDR2_CB3 DIMM1_DDR2_CB2 DIMM1_DDR2_CB1 DIMM1_DDR2_CB0 DIMM1_DDR2_CAS_B DIMM1_DDR2_BA2 DIMM1_DDR2_BA1 DIMM1_DDR2_BA0 DIMM1_DDR2_A13 DIMM1_DDR2_A12 DIMM1_DDR2_A11 DIMM1_DDR2_A10 DIMM1_DDR2_A9 DIMM1_DDR2_A8 DIMM1_DDR2_A7 DIMM1_DDR2_A6 DIMM1_DDR2_A5 ...
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Chapter 1: ML510 Embedded Development Platform Figure 1-4 X-Ref Target - Figure 1-4 10/100/1000 Tri-Speed Ethernet PHY The board contains two Marvell Alaska PHY devices (88E1111) operating at 10/100/1000 Mb/s. The board supports MII, RGMII, and SGMII interface modes on ...
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... RGMII ML510 Embedded Development Platform UG356 (v1.1 ) December 11, 2008 Bit[2] Definition and Value Definition and Value ANEG[ ANEG[ ANEG[ ENA_XC = 1 HWCFG_MODE[ HWCFG_MODE[ (Set by J23 and J24) DIS_FC = 1 DIS_SLEEP = 1 SEL_BDT = 0 INT_POL = 1 and Table 1-7). The interface can also be changed via MDIO commands. ...
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Chapter 1: ML510 Embedded Development Platform Figure 1-6 X-Ref Target - Figure 1-6 Figure 1-7 X-Ref Target - Figure 1-7 28 shows the PHY0 MII interface. FPGA PHY0_TXCLK PHY0_TXER PHY0_TXCTL_TXEN PHY0_TXD[3:0] PHY0_RXCLK PHY0_RXER PHY0_RXCTL_RXDV PHY0_RXD[3:0] PHY0_RESET PHY0_INT PHY0_MDC PHY0_MDIO Figure ...
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R Figure 1-8 X-Ref Target - Figure 1-8 Table 1-8: PHY0 MII/RGMII/SGMII Interfaces Signal Name PHY0_TX_CLK PHY0_RXC_CLK PHY0_GTX_CLK PHY0_TXD3 PHY0_TXD2 PHY0_TXD1 PHY0_TXD0 PHY0_TXER PHY0_TXCTL_TXEN PHY0_RX_D3 PHY0_RX_D2 PHY0_RX_D1 PHY0_RX_D0 ML510 Embedded Development Platform UG356 (v1.1 ) December 11, 2008 shows the ...
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Chapter 1: ML510 Embedded Development Platform Table 1-8: PHY0 MII/RGMII/SGMII Interfaces (Cont’d) Signal Name PHY0_RXER PHY0_RXCTL_RXDV PHY0_SGMII_TX_P PHY0_SGMII_TX_N PHY0_SGMII_RX_P PHY0_SGMII_RX_N PHY0_INT PHY0_RESET PHY0_MDIO PHY0_MDC Table 1-9: PHY1 SGMII Interface Signal Name PHY1_SGMII_TX_P PHY1_SGMII_TX_N PHY1_SGMII_RX_P PHY1_SGMII_RX_N PHY1_INT PHY1_RESET PHY1_MDIO PHY1_MDC SGMIICLK_P ...
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R System ACE and CompactFlash Connector The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I CompactFlash card to program the FPGA through the JTAG port. Both hardware and software data can be downloaded through the JTAG port. ...
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Chapter 1: ML510 Embedded Development Platform Board Bring-Up through the JTAG Interface The System ACE CF controller is located between the JTAG connector and the FPGA, and passes the JTAG signals back and forth between the two. During configuration, the ...
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R The JTAG configuration port on the System ACE CF controller is connected directly to the JTAG interface of the FPGA, as shown in Table 1-10: JTAG Connection from System ACE CF to FPGA Signal Name FPGA_TCK FPGA_TDO FPGA_TDI FPGA_TMS ...
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Chapter 1: ML510 Embedded Development Platform Table 1-11: System ACE MPU Connection from FPGA to Controller (Cont’d) Signal Name SYSACE_MPD10 sysace_mpd11 sysace_mpd12 sysace_mpd13 sysace_mpd14 sysace_mpd15 sysace_mpoe sysace_mpce sysace_mpwe sysace_mpirq Linear Flash Memory A 16-bit wide NOR linear flash device (Intel ...
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R X-Ref Target - Figure 1-11 FPGA FLASH_A0 A0 FLASH_A1 A1 FLASH_A2 A2 FLASH_A20 A20 FLASH_A21 A21 A22 AK14 RS0 AK13 RS1 AK12 32 MB BPI Flash Use RS[0:1] to select bit files This configuration allows ...
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Chapter 1: ML510 Embedded Development Platform Table 1-12: Linear Flash Connection from FPGA to Strata Flash (U43) (Cont’d) Signal Name FLASH_D8 FLASH_D7 FLASH_D6 FLASH_D5 FLASH_D4 FLASH_D3 FLASH_D2 FLASH_D1 FLASH_D0 FLASH_CLK FLASH_CE_B FLASH_ADV_B FLASH_A21 FLASH_A20 FLASH_A19 FLASH_A18 FLASH_A17 FLASH_A16 FLASH_A15 FLASH_A14 ...
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R GPIO LEDs and LCD ML510 platforms provide direct GPIO access to eight LEDs for general purpose use, and provide indirect access to a 16-pin connector (J13) that interfaces the FPGA to a 2-line by 16-character LCD display, AND491GST. A ...
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Chapter 1: ML510 Embedded Development Platform GPIO LED Interface All LEDs connected to the GPIO lines illuminate green when driven with a logic 0 and extinguish with a logic 1. FPGA to the non-inverting buffer (U36). The FPGA GPIO lines ...
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R The control signals allow the user to read/write the LCD character display in conjunction with the eight LCD data signals defined in data sheet located on the ML510 documentation CD for more information. Table 1-15 shows the control signal ...
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Chapter 1: ML510 Embedded Development Platform X-Ref Target - Figure 1-13 2.5V Table 1-16 shows the CPU trace/debug connections from P8 to the FPGA. Table 1-16: CPU Trace/Debug Connection to FPGA Pin Name - - - - ATCB_CLK TRC_CLK CPU_HALT_B ...
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R Table 1-16: CPU Trace/Debug Connection to FPGA (Cont’d) Pin Name - CPU_TCK ATD_4 CPU_TMS ATD_3 CPU_TDI ATD_2 CPU_TRST_B ATD_1 ATD_0 TRC_ES4 TRC_BS0_BR0 TRC_TSO TRC_BS1_BR1 TRC_TS1 TRC_BS2_BR2 TRC_TS2 TRC_ES0 TRC_TS3 TRC_ES1 TRC_TS4 TRC_ES2 TRC_TS5 TRC_ES3 TRC_TS6 ML510 Embedded Development Platform ...
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Chapter 1: ML510 Embedded Development Platform CPU JTAG Header Pinout Figure 1-14 in the CPU with debug tools such as Parallel Cable IV or third party tools. X-Ref Target - Figure 1-14 CPU JTAG Connection to FPGA The connections between ...
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R The DVI connector monitor’s configuration parameters. These parameters can be read by the FPGA using the VGA IIC bus. Table 1-18: DVI Controller Connections Net Name DVI_D0 DVI_D1 DVI_D2 DVI_D3 DVI_D4 DVI_D5 DVI_D6 DVI_D7 DVI_D8 DVI_D9 DVI_D10 DVI_D11 DVI_XCLK_P ...
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Chapter 1: ML510 Embedded Development Platform X-Ref Target - Figure 1-15 +3.3 IIC_SCL IIC_SDA +12V 25 MHz Table 1-19 and Express connectors. Table 1-19: Connections from FPGA to PCI Express Slot A GTP122_PCIE_SLOTA_CLK_P GTP122_PCIE_SLOTA_CLK_N GTP126_PCIE_SLOTA_CLK_P GTP126_PCIE_SLOTA_CLK_N PCIE_SLOTA_WAKE_B_R PCIE_SLOTA_PRSNT2_B_R PCIE_SLOTA_PERST_B GTP_122_TX0_P_C ...
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R Table 1-19: Connections from FPGA to PCI Express Slot A (Cont’d) GTP_122_RX1_P GTP_122_RX1_N GTP_126_TX0_P_C GTP_126_TX0_N_C GTP_126_RX0_P GTP_126_RX0_N GTP_126_TX1_P_C GTP_126_TX1_N_C GTP_126_RX1_P GTP_126_RX1_N GTP_130_TX0_P_C GTP_130_TX0_N_C GTP_130_RX0_P GTP_130_RX0_N GTP_130_TX1_P_C GTP_130_TX1_N_C GTP_130_RX1_P GTP_130_RX1_N Table 1-20: Connections from FPGA to PCI Express Slot B ...
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Chapter 1: ML510 Embedded Development Platform Table 1-20: Connections from FPGA to PCI Express Slot B (Cont’d) GTP_128_TX1_N_C GTP_128_RX1_P GTP_128_RX1_N GTP_132_TX0_P_C GTP_132_TX0_N_C GTP_132_RX0_P GTP_132_RX0_N GTP_132_TX1_P_C GTP_132_TX1_N_C GTP_132_RX1_P GTP_132_RX1_N PCI Bus ML510 platforms provide the FPGA with access to two 33 ...
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R In addition to the fixed PCI devices, there are four 33 MHz, 32-bit PCI slots available for use. For more information on the PCI slot pinouts, refer to the PCI Local Bus Specification, Revision 2.2 and the ML510 schematics. ...
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Chapter 1: ML510 Embedded Development Platform Table 1-21 along with information for each device. Table 1-21: 3.3V Primary PCI Bus Information Vend. Device Name Dev PCI Slot 5 N/A N/A PCI Slot 3 N/A N/A U15, ALi SB ...
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R ALi South Bridge Interface, M1535D+ (U15) The ALi M1535D+ South Bridge Super I/O controller with many of the basic features found on legacy PCs. These basic PC features are only accessible over the PCI bus because this is the ...
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Chapter 1: ML510 Embedded Development Platform USB Connector Assembly (J3) The M1535D+ USB is an implementation of the Universal Serial Bus Specification Version 1.0a (see www.usb.org) that contains two PCI Host Controllers and an integrated Root Hub. The two USB ...
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R Table 1-24: ALi South Bridge IDE Connections (Cont’d) IDE Primary Pin (J16 System Management Bus Controller ...
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Chapter 1: ML510 Embedded Development Platform AC’97 Audio Interface The ALi South Bridge Super I/O controller has a built-in audio interface that is combined with a standard audio codec (AC’97), LM4550. Available features include: ♦ AC’97 Codec 2.1 Specification compliant ...
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R Table 1-26 shows the PS/2 keyboard and mouse connections to the P2 connector assembly. Table 1-26: PS/2 Keyboard and Mouse Signal Name KDAT KCLK MDAT MCLK KVCC, MVCC IIC/SMBus Interface Introduction to IIC/SMBus The Inter Integrated Circuit (IIC) bus ...
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Chapter 1: ML510 Embedded Development Platform Figure 1-18 the IIC bus. Note: Either the FPGA or the ALi M1535D+ can master the IIC bus, but not simultaneously. X-Ref Target - Figure 1-18 FPGA (U37) 54 shows a block diagram of ...
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R Table 1-28 Table 1-28: IIC Devices and Addresses Device LTC1694 RTC8564 24LC64 LM87 MIC2592B DDR2_DIMM0 DDR2_DIMM1 Header DVI Output: Codec IC Notes: 1. The IIC bus can be controlled directly by the FPGA or indirectly by the ALi bridge ...
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Chapter 1: ML510 Embedded Development Platform • Serial Clock (SCK): A control line driven by the master device to regulate the flow of data and enable a master to transmit data at a variety of baud rates ♦ The SCK ...
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R FPGA to Serial ATA Connector ML510 platforms that are equipped with RocketIO transceivers provide for operation as a Serial ATA host or device. These connections are also shown in Table 1-30: Connections Between FPGA and Serial ATA Connector (J25 ...
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Chapter 1: ML510 Embedded Development Platform CPU Reset (SW2) SW2 is a manual pushbutton reset switch for the PPC440 system implemented in the FPGA. To use this switch, the user must connect the PB_FPGA_CPU_RESET signal to the PPC440 system within ...
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R ♦ FPGA configuration DONE output ♦ IDE disk access output ♦ ATX power output ♦ Two FPGA user-defined output signals ♦ ATX speaker output ♦ Keyboard inhibit input (active-Low) Note: All front panel interface outputs, except for the speaker ...
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Chapter 1: ML510 Embedded Development Platform Table 1-31: Front Panel Interface Connector (J23) (Cont’d) J23 Pin 21 PB_SYSACE_RESET 22 GND 23 PB_FPGA_CPU_RESET 24 GND Jumpers Note: Pins should only be jumpered with the board powered off. 12V Fan (J7) Table ...
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R I/O Voltage Margining (J24 and J37) The voltage margins on the board can be adjusted by shorting the jumpers as shown in Table 1-34. Apply shorting jumpers only when the board is powered off. For more on voltage regulation, ...
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Chapter 1: ML510 Embedded Development Platform ATX Power Distribution and Voltage Regulation ML510 platforms are shipped with a commercially available 250W ATX power supply. All voltages required by the ML510 logic devices are derived from the 5V supply, except the ...
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R Voltage monitors connected to power indicator LEDs monitor the regulated power on the board (see out of spec, and illuminate green if the regulated supply voltage is nominal. Each regulated supply voltage has a corresponding test point located near ...
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Chapter 1: ML510 Embedded Development Platform Table 1-35 Table 1-35: Voltage Monitor Information Schematic Net Name VCC1V0 VCC1V8 VCC2V5 VCC3_PCI VCC3V3 VCC5V VTT_DDR2 VTTDDR AVCCAUXMGT VCC12V_P VCC12V_N Notes: 1. Green LED = Voltage Nominal; Red LED = Voltage Fault System ...
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R called Over-Temperature (OT) if the FPGA temperature becomes critical (> 125°C). The OT signal is deactivated when the device temperature falls below a user specified lower limit. If the FPGA power-down feature is enabled, the FPGA enters power down ...
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Chapter 1: ML510 Embedded Development Platform Table 1-36: System Monitor Header (J33) (Cont’d) J33 Pin 5 GND 6 GND 7 ADR_VREFP 8 TEST_MON_AVDD 9 TEST_MON_VN0_N 10 TEST_MON_VN0_P 11 CURRENT_SENSE_OUT 12 CURRENT_SENSE_REG Notes: 1. Default setting = jumper over pins 1-2 ...
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R development platform, is referred to as the host board connector; the receptacle, located on the personality module, is referred to as the adapter board connector. X-Ref Target - Figure 1-23 Figure 1-23: Personality Module Connected to Embedded Development Platform ...
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Chapter 1: ML510 Embedded Development Platform side to side along the length of the divider. All of the B and E pins are grounded on the ML510. The and F pins are signal pins. X-Ref Target - ...
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R PM1 Connector The PM1 connector provides the following signals: • 8 RocketIO 4.25 Gb/s transceivers • 3 LVDS pairs at 2.5V (can be used as 6 single-ended I/O at 2.5V) • 1 LVDS clock pair at 2.5V • 12 ...
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Chapter 1: ML510 Embedded Development Platform Z-DOK+ Utility Pins Figure 1-27 connector. X-Ref Target - Figure 1-27 Figure 1-28 connector. X-Ref Target - Figure 1-28 Note: The pins on the adapter board connector are at varying heights, as shown in ...
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R PM1 Power and Ground Table 1-39 Table 1-39: PM1 Power and Ground Pins Pin Number User I/O Pins PM1 User I/O The PM1 connector makes the GTX signals from the eight RocketIO ...
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Chapter 1: ML510 Embedded Development Platform Table 1-40: PM1 Pinout (Cont’d) PM1 Pin FPGA Pin A19 A20 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 ...
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R Table 1-40: PM1 Pinout (Cont’d) PM1 Pin FPGA Pin D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 ...
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Chapter 1: ML510 Embedded Development Platform PM2 User I/O The PM2 connector makes most of the LVDS pairs available to the user, along with single- ended signals. Table 1-41: PM2 Pinout PM2 Pin FPGA Pin ...
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R Table 1-41: PM2 Pinout (Cont’d) PM2 Pin FPGA Pin C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D10 D11 D12 D13 D14 ML510 Embedded ...
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Chapter 1: ML510 Embedded Development Platform Table 1-41: PM2 Pinout (Cont’d) PM2 Pin FPGA Pin D15 D16 D17 D18 D19 D20 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 ...
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R Configuration Options The FPGA on the ML510 Evaluation Platform can be configured by the following major devices: • Xilinx download cable (JTAG) • System ACE controller (JTAG) • Linear Flash memory byte peripheral interface (BPI) The following section provides ...
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Chapter 1: ML510 Embedded Development Platform System ACE Controller Configuration SW3 is a three position DIP switch that controls the three configuration address pins on the System ACE CF controller. The addresses, CFGADDR0, CFGADDR1, and CFGADDR2, are marked on SW3 ...
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R Linear Flash Memory Configuration Data stored in the linear flash can be used to program the FPGA (BPI mode four configuration images can theoretically be supported. SW3 BPI default settings: • CFGA[2:0] 000 (0x0) • MODE[2:0] 010 ...
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Chapter 1: ML510 Embedded Development Platform 80 www.xilinx.com ML510 Embedded Development Platform UG356 (v1.1 ) December 11, 2008 R ...
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R References This section provides references to documentation supporting Virtex-5 devices, tools, and IP. For additional information, see www.xilinx.com/support/documentation/index.htm. Documents supporting Virtex-5 FPGAs: 1. DS100, Virtex-5 Family Overview. 2. DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristics. 3. UG190, ...
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DS551, LogiCORE Endpoint Block Plus for PCI Express Data Sheet. 25. UG341, LogiCORE Endpoint Block Plus for PCI Express User Guide. 26. UG343, LogiCORE Endpoint Block Plus for PCI Express Getting Started Guide. Documents supporting the LogiCORE SGMII solution: ...