HW-V5-ML510-G Xilinx Inc, HW-V5-ML510-G Datasheet - Page 17

• Manufacturer Part Number: HW-V5-ML510-G
• Description: BOARD EVAL FOR VIRTEX-5 ML510
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-ML510-G

• Contents: Evaluation Board
• Kit Contents: ML510 Board (ATX Form Factor), 512 MB CompactFlash Card, Two 512 MB DDR2 DIMMs, LCD Display, Cable
• Svhc: No SVHC (15-Dec-2010)
• Development Tool Type: Hardware / Software - Dev Kit
• Silicon Manufacturer: Xilinx
• Core Architecture: Virtex
• Silicon Family Name: Virtex-5
• Features: VGA Graphics Interface, Fan
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ML510 Embedded Development Platform
UG356 (v1.1 ) December 11, 2008
R
Dual DDR2 SDRAM DIMMs
The board’s DDR2 memory interfaces are designed to the requirements defined by the
Xilinx Memory Interface Generator (MIG) User Guide
MIG documentation requires that designers follow the MIG pinout and layout guidelines.
The MIG tool generates and ensures that the proper FPGA I/O pin selections are made in
support of the board’s DDR2 interfaces. The initial pin selection for the board was
modified and then re-verified to meet the MIG pinout requirements. To ensure a robust
interface, the ML510 DDR2 layout incorporates matched trace lengths for data signals to
the corresponding data strobe signal as defined in the MIG user guide. See
“References”
general.
The DDR2 DIMMs are standard 240-pin DIMM sockets, supporting standard computer
DDR2 memory.
ML510 boards are shipped with dual single-rank registered 512 MB PC2-5300 DDR2-667
DIMMs. The DDR2 DIMM is commercially available from Wintec Industries. The DDR2
DIMM uses nine 32M x 8 DDR2 SDRAM devices with 14-row address lines, 10-column
address lines, and two bank address lines. Read and write access is programmable in burst
lengths of 4 or 8. The memory module inputs and outputs are compatible with SSTL18
signaling. Serial Presence Detect (SPD) using an IIC interface to the DDR DIMM is also
supported. See the
module’s SPD EEPROM.
The DDR2 DIMM memory interface includes a 72-bit wide datapath to the DDR2 DIMM,
which includes 8 bits for ECC.
DDR2 Memory Expansion
The DDR2 interface is very flexible and can accommodate different DDR2 memory
requirements, such as increased memory size. Please review the Embedded Processor Block in
Virtex-5 FPGAs Reference Guide
DDR2 Clock Signal
The DDR2 clock signal is broadcast from the FPGA as a single differential pair that drives
a clock fan-out chip, which then drives the DDR2 DIMM. The delay on the clock trace is
designed to match the delay of the other DDR2 control and data signals. The DDR2 clock
is also fed back to the FPGA to allow for clock deskew using Virtex-5 DCMs. The board is
designed so that the DDR2 clock signal reaches the FPGA clock feedback pin at the same
time as it arrives at the DDR2 DIMM. This clock fanout circuit is duplicated for both DIMM
interfaces.
DDR2 Signaling
Only DDR2 SDRAM control signals are terminated through 47Ω resistors to a 0.9V VTT
reference voltage. The board is designed for matched length traces across all DDR2 control
and data signals, except clocks. The FPGA DDR2 interface supports SSTL18 signaling. All
DDR2 signals are controlled impedance and are SSTL18 at the DIMM via ODT and at the
FPGA via DCI.
for links to additional information about MIG and Virtex-5 FPGAs in
“IIC/SMBus Interface”
www.xilinx.com
[Ref 4]
when migrating to a different DDR2 DIMM.
section for more details on accessing the DIMM
[Ref 21]
using the MIG tool
Detailed Description
Appendix A,
[Ref
23]. The
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