HW-V5-ML510-G Xilinx Inc, HW-V5-ML510-G Datasheet - Page 5
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HW-V5-ML510-G
Manufacturer Part Number
HW-V5-ML510-G
Description
BOARD EVAL FOR VIRTEX-5 ML510
Manufacturer
Xilinx Inc
Series
Virtex™ -5r
Type
FPGAr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.HW-V5-ML510-G.pdf
(82 pages)
Specifications of HW-V5-ML510-G
Contents
Evaluation Board
Kit Contents
ML510 Board (ATX Form Factor), 512 MB CompactFlash Card, Two 512 MB DDR2 DIMMs, LCD Display, Cable
Svhc
No SVHC (15-Dec-2010)
Development Tool Type
Hardware / Software - Dev Kit
Silicon Manufacturer
Xilinx
Core Architecture
Virtex
Silicon Family Name
Virtex-5
Features
VGA Graphics Interface, Fan
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Virtex™-5 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
RocketIO GTP Transceivers (LXT/SXT only)
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RocketIO GTX Transceivers (TXT/FXT only)
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DS100 (v5.0) February 6, 2009
Product Specification
Full-duplex serial transceiver capable of 100 Mb/s to
3.75 Gb/s baud rates
8B/10B, user-defined FPGA logic, or no encoding
options
Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
Programmable termination and voltage swing
Programmable equalization for the receiver
Receiver signal detect and loss of signal indicator
User dynamic reconfiguration using secondary
configuration bus
Out of Band (OOB) support for Serial ATA (SATA)
Electrical idle, beaconing, receiver detection, and PCI
Express and SATA spread-spectrum clocking support
Less than 100 mW typical power consumption
Built-in PRBS Generators and Checkers
Full-duplex serial transceiver capable of 150 Mb/s to
6.5 Gb/s baud rates
8B/10B encoding and programmable gearbox to
support 64B/66B and 64B/67B encoding, user-defined
FPGA logic, or no encoding options
Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
Programmable termination and voltage swing
Programmable continuous time equalization for the
receiver
Programmable decision feedback equalization for the
receiver
Receiver signal detect and loss of signal indicator
User dynamic reconfiguration using secondary
configuration bus
OOB support (SATA)
Electrical idle, beaconing, receiver detection, and
PCI Express spread-spectrum clocking support
Low-power operation at all line rates
R
www.xilinx.com
PowerPC 440 RISC Cores (FXT only)
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Embedded PowerPC 440 (PPC440) cores
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Integrated crossbar for enhanced system performance
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Auxiliary Processor Unit (APU) Interface and Controller
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Up to 550 MHz operation
Greater than 1000 DMIPS per core
Seven-stage pipeline
Multiple instructions per cycle
Out-of-order execution
32 Kbyte, 64-way set associative level 1 instruction
cache
32 Kbyte, 64-way set associative level 1 data cache
Book E compliant
128-bit Processor Local Buses (PLBs)
Integrated scatter/gather DMA controllers
Dedicated interface for connection to DDR2 memory
controller
Auto-synchronization for non-integer PLB-to-CPU clock
ratios
Direct connection from PPC440 embedded block to
FPGA fabric-based coprocessors
128-bit wide pipelined APU Load/Store
Support of autonomous instructions: no pipeline stalls
Programmable decode for custom instructions
Virtex-5 Family Overview
5