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HW-V4-ML410-UNI-G Summary of contents
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ML410 Embedded Development Platform User Guide UG085 (v1.7.2) December 11, 2008 R ...
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
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Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Additional Resources Conventions . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction to the System ACE Configuration Solution Board Bring-Up through the JTAG Interface Non-Volatile Storage through the MPU Interface GPIO LEDs and LCD . . . . . . . . . . . . . . . . . ...
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R Appendix A: Board Revisions Appendix B: References ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 www.xilinx.com 5 ...
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ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 R ...
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Schedule of Figures Chapter 1: Introduction to Virtex-4, ISE, and EDK Chapter 2: ML410 Embedded Development Platform Figure 2-1: ML410 High-Level Block Diagram . . . . . . . . . . . . . . . . . ...
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ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 R ...
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Schedule of Tables Chapter 1: Introduction to Virtex-4, ISE, and EDK Table 1-1: Virtex-4 FX Family Members . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 2-35: IIC and SMBus Controller Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table ...
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R About This Guide This manual accompanies the ML410 series of Embedded Development Platforms and contains information about the ML410 hardware and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “Introduction to Virtex-4, ISE, and ...
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Preface: About This Guide Convention Courier font Courier bold Helvetica bold Italic font Square brackets [ ] Braces { } Vertical bar | Vertical ellipsis . . . Horizontal ellipsis . . . Online Document The following conventions are used ...
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R Convention Red text Blue, underlined text ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Meaning or Use Cross-reference link to a location See in another document Platform FPGA User Guide Hyperlink to a website (URL) for ...
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Preface: About This Guide 14 www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 R ...
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R Introduction to Virtex-4, ISE, and EDK Virtex-4 FPGAs Virtex®-4 domain-optimized FPGAs provide an ideal mix of features and the greatest choice of devices of any FPGA product line on the market today, with a column-based architecture unique to the ...
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Chapter 1: Introduction to Virtex-4, ISE, and EDK ♦ Built-in ChipSync™ source-synchronous technology ♦ Digitally-controlled impedance (DCI) active termination ♦ Fine grained I/O banking (configuration in one bank) • Flexible logic resources • Secure Chip AES bitstream encryption • 90 ...
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R RocketIO Transceivers • Full-duplex serial transceiver (SERDES) capable of running 622 Mb/s - 6.5 Gb/s Note: details. • Full clock and data recovery • 32-bit or 40-bit datapath support • Optional 8B/10B, 64B/66B, or FPGA-based encode/decode • Integrated FIFO/elastic ...
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Chapter 1: Introduction to Virtex-4, ISE, and EDK This rich mixture of design entry capabilities provides the easiest to use design environment available today for your logic design. Synthesis Synthesis is one of the most essential steps in your design ...
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R • IBIS models • HSPICE models • STAMP models Embedded Development Kit The Embedded Development Kit (EDK series of software tools for designing embedded processor systems on programmable logic and supports the IBM PowerPC hard processor core ...
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Chapter 1: Introduction to Virtex-4, ISE, and EDK 20 www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 R ...
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R ML410 Embedded Development Platform Overview The ML410 series of Embedded Development Platforms offer designers a versatile Virtex-4 FX platform for rapid prototyping and system verification. In addition to the more than 30,000 logic cells, over 2,400 kb of block ...
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Chapter 2: ML410 Embedded Development Platform • LEDs, LCD*, and switches • 32/33 PCI subsystem ♦ Two 3.3V slots and two 5V slots ♦ ALi South Bridge SuperIO controller - - - - - • Two serial ATA connectors • ...
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R Block Diagram Figure 2-1 Flash GPIO 2x IDE 2x USB Related Xilinx Documents Prior to using the ML410 Embedded Development Platform, users should be familiar with Xilinx resources. See See the following locations for additional documentation on Xilinx tools ...
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Chapter 2: ML410 Embedded Development Platform Detailed Description The ML410, shown in guide. Prog Pushbutton, SW4 System ACE Status and Error LEDs System ACE Configuration DIP Switch, SW3 Power-On Front Panel Header, J23 Switch CPU JTAG Header, J12 LCD Interface ...
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R Configuration ML410 platforms support configuration in JTAG mode only. Configuration can be accomplished by using a Xilinx download cable (such as Parallel Cable IV or Platform Cable USB using the onboard System ACE CompactFlash solution. See ACE ...
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Chapter 2: ML410 Embedded Development Platform Table 2-2: DCI Capability of FPGA Bank (Cont’d) FPGA Bank 4 Not supported 5 Yes, 49.9 6 Yes, 49.9 Clock Generation ML410 boards are equipped with two crystal oscillator sockets (X6 and X10) each ...
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R Figure 2-3 earlier revisions of the ML410 platform, see X6 100 MHz (OSC in Socket) X10 Empty Socket X8 33 MHz OE J17 J36 U48 CLK100_Q0 CLK100_NQ0 X5 100 MHz (LVPECL) 25 MHz ICS843001 ICS8740031-02 MGT_SMA_CLK_P J20 MGT_SMA_CLK_N J21 ...
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Chapter 2: ML410 Embedded Development Platform Table 2-3 shows the ML410 clock connections. Table 2-3: Clock Connections Schematic Net Name USER_CLKSYS USER_CLK2 USER_SMA_CLK_N USER_SMA_CLK_P PM_CLK_TOP PM_CLK_BOT LVDS_CLKEXT_P LVDS_CLKEXT_N SGMIICLK_Q0 SGMIICLK_NQ0 MGTCLK_P_110 MGTCLK_N_110 SATACLK_Q0 SATACLK_NQ0 Notes: 1. See “High-Speed I/O,” page ...
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R DDR and DDR2 Memory ML410 platforms have two types of double data rate (DDR) memory, two component DDRs and a DDR2 SDRAM DIMM. The two memory systems are independent and enable users to build independent systems. DDR Component Memory ...
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Chapter 2: ML410 Embedded Development Platform Table 2-4 lists the connections from the FPGA to the DDR interface. Note that the DDR1_DQ signal names do not correlate as the FPGA uses IBM notation, big endian, while the DDR components use ...
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R Table 2-4: Connections from FPGA to DDR1 SDRAMs (U42 and U43) (Cont’d) UCF Signal Name DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31] DDR1_CS_N DDR1_CKE DDR1_LOOP DDR1_LOOP DDR1_CK1_P DDR1_CK1_N DDR1_CLK_FB DDR1_BA[0] DDR1_BA[1] DDR1_A[0] ...
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Chapter 2: ML410 Embedded Development Platform Table 2-4: Connections from FPGA to DDR1 SDRAMs (U42 and U43) (Cont’d) UCF Signal Name DDR1_A[9] DDR1_A[10] DDR1_A[11] DDR1_A[12] DDR1_A[13] DDR2 SDRAM DIMM The DDR2 DIMM is a standard 240-pin DIMM socket, supporting standard ...
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R Table 2-5 describes all the signals associated with DDR2 DIMM component memories. Note that the DDR2_DQ signal names do not correlate because the FPGA uses IBM notation, big endian, while the DDR2 DIMM uses Intel notation, little endian. Table ...
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Chapter 2: ML410 Embedded Development Platform Table 2-5: Connections from FPGA to DDR2 DIMM Interface (P48) (Cont’d) UCF Signal Name DDR2_A[7] DDR2_A[8] DDR2_A[9] DDR2_A[10] DDR2_A[11] DDR2_A[12] DDR2_A[13] DDR2_BA[0] DDR2_BA[1] DDR2_CK0 DDR2_CK0_N DDR2_CS0_N DDR2_CKE0 DDR2_DM[0] DDR2_DM[1] DDR2_DM[2] DDR2_DM[3] DDR2_DM[4] DDR2_DM[5] DDR2_DM[6] ...
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R Table 2-5: Connections from FPGA to DDR2 DIMM Interface (P48) (Cont’d) UCF Signal Name DDR2_DQ[11] DDR2_DQ[12] DDR2_DQ[13] DDR2_DQ[14] DDR2_DQ[15] DDR2_DQ[16] DDR2_DQ[17] DDR2_DQ[18] DDR2_DQ[19] DDR2_DQ[20] DDR2_DQ[21] DDR2_DQ[22] DDR2_DQ[23] DDR2_DQ[24] DDR2_DQ[25] DDR2_DQ[26] DDR2_DQ[27] DDR2_DQ[28] DDR2_DQ[29] DDR2_DQ[30] DDR2_DQ[31] DDR2_DQ[32] DDR2_DQ[33] DDR2_DQ[34] DDR2_DQ[35] ...
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Chapter 2: ML410 Embedded Development Platform Table 2-5: Connections from FPGA to DDR2 DIMM Interface (P48) (Cont’d) UCF Signal Name DDR2_DQ[43] DDR2_DQ[44] DDR2_DQ[45] DDR2_DQ[46] DDR2_DQ[47] DDR2_DQ[48] DDR2_DQ[49] DDR2_DQ[50] DDR2_DQ[51] DDR2_DQ[52] DDR2_DQ[53] DDR2_DQ[54] DDR2_DQ[55] DDR2_DQ[56] DDR2_DQ[57] DDR2_DQ[58] DDR2_DQ[59] DDR2_DQ[60] DDR2_DQ[61] DDR2_DQ[62] ...
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R Figure 2-5 FPGA (U37) System Clk DDR Device CLKIN CLK0 External Clk CLKFB CLK90 CLKDV DCM 200 MHz Clk Tri-Mode (10/100/1000 Mb/s) Ethernet PHY ML410 platforms feature two Ethernet PHYs that support MII, RGMII, and SGMII interfaces, as shown ...
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Chapter 2: ML410 Embedded Development Platform PHY0: MII/RGMII PHY0 (U60) is configured at power-on or reset to the default settings shown in PHY0 is configurable to MII, or RGMII modes through the J28 jumper settings, as shown in Figure 2-6. ...
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R Figure 2-7 shown in bold text to indicate the behavior of the signals on each interface. ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 and Figure 2-8 show the MII and RMII interfaces. Functional differences are FPGA PHY_TXCLK ...
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Chapter 2: ML410 Embedded Development Platform Table 2-8 shows the MII/RGMII interface for PHY0. Table 2-8: PHY0 MII/RGMII Interface Signal Name PHY_TXCLK PHY_RXC_RXCLK PHY_GTXCLK PHY_TXD3 PHY_TXD2 PHY_TXD1 PHY_TXD0 PHY_TXER PHY_TXCTL_TXEN PHY_RXD3 PHY_RXD2 PHY_RXD1 PHY_RXD0 PHY_RXER PHY_RXCTL_RXDV PHY_INT PHY_RESET PHY_MDIO PHY_MDC ...
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R PHY1: SGMII Table 2-9 shows the default configuration settings for PHY1 (U61). PHY1 is fixed to SGMII mode only. It connects directly to the RocketIO transceiver not software selectable. Table 2-9: PHY1 (U61) Configuration Settings for ...
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Chapter 2: ML410 Embedded Development Platform 42 SGMII Interface FPGA PHY1_TXD_P PHY1_TXD_N PHY1_RXD_P PHY1_RXD_N PHY1_MDC PHY1_MDIO Figure 2-9: SGMII Interface www.xilinx.com ML410 Embedded Development Platform R PHY (U61) UG085_09_111505 UG085 (v1.7.2) December 11, 2008 ...
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R RS-232 Ports Two RS-232 ports, shown in independent MAX3232 transceivers (U7 and U46). The FPGA RS-232 ports are wired as DTE and meet the EIA/TIA-574 standard. The ports are accessible via two DB9M connectors integrated on the P1 connector ...
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Chapter 2: ML410 Embedded Development Platform Table 2-13: FPGA RS-232 Connections for UART1 Signal Name UART1_CTS_N UART1_RTS_N UART1_RXD UART1_TXD System ACE CF Controller Introduction to JTAG JTAG (Joint Test Action Group simple interface that provides for many uses. ...
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generic FAT file system. The data bus for the System ACE MPU port is shared with the USB controller. See Board Bring-Up through the JTAG Interface The System ACE CF controller is located between the JTAG connector ...
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Chapter 2: ML410 Embedded Development Platform The pinout shown in programming solution. The J9 header is used when programming the FPGA by way of the PC4 download cable. The JTAG configuration port on the System ACE CF controller is connected ...
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R Table 2-15: System ACE MPU Connection from FPGA to Controller (Cont’d) UCF Signal Name SYSACE_MPA[5] SYSACE_MPA[6] SYSACE_MPD[0] SYSACE_MPD[1] SYSACE_MPD[2] SYSACE_MPD[3] SYSACE_MPD[4] SYSACE_MPD[5] SYSACE_MPD[6] SYSACE_MPD[7] SYSACE_MPD[8] SYSACE_MPD[9] SYSACE_MPD[10] SYSACE_MPD[11] SYSACE_MPD[12] SYSACE_MPD[13] SYSACE_MPD[14] SYSACE_MPD[15] SYSACE_MPOE SYSACE_MPCE SYSACE_MPWE SYSACE_MPIRQ GPIO LEDs and ...
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Chapter 2: ML410 Embedded Development Platform Figure 2-13 VCC3V3 Non-Inverting Buffer (U36) 20 VCCA 1 1OE 2 DBG_LED_0 1A1 4 DBG_LED_1 1A2 6 DBG_LED_2 1A3 8 DBG_LED_3 1A4 19 2OE 11 DBG_LED_4 2A1 13 DBG_LED_5 2A2 15 DBG_LED_6 2A3 17 ...
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R GPIO LED Interface All LEDs connected to the GPIO lines illuminate green when driven with a logic 0 and extinguish with a logic 1. FPGA to the non-inverting buffer (U36). Table 2-16: GPIO LED Connection from FPGA to U36 ...
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Chapter 2: ML410 Embedded Development Platform Table 2-18 Table 2-18: GPIO LCD Control Signals from FPGA to U33 UCF Signal Name FPGA_LCD_E FPGA_LCD_RS FPGA_LCD_RW CPU Debugging Interfaces ML410 platforms include two optional CPU debugging interfaces: the combined FPGA JTAG/TRACE (P8) ...
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R support the attachment of debug tools. These enhancements comply with the IEEE 1149.1 specifications for vendor-specific extensions and are compatible with standard JTAG hardware for boundary-scan system testing. The PPC405 JTAG debug port supports the four required JTAG signals: ...
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Chapter 2: ML410 Embedded Development Platform Table 2-19: CPU Trace/Debug Connection to FPGA (Cont’d) Pin Name ATCB_CLK TRC_CLK CPU_HALT_N - - - CPU_TDO TRC_VSENSE - - CPU_TCK - CPU_TMS ATD_18 CPU_TDI ATD_17 CPU_TRST_N ATD_16 ATD_15 TRC_TS1O ATD_14 TRC_TS2O ATD_13 TRC_TS1E ...
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R Table 2-19: CPU Trace/Debug Connection to FPGA (Cont’d) Pin Name ATD_8 TRC_TS6 CPU JTAG Header Pinout Figure 2-15 in the CPU with debug tools such as Parallel Cable IV or third party tools. Refer to the PowerPC 405 Processor ...
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Chapter 2: ML410 Embedded Development Platform VGA Output A VGA DB15HD connector (P2) is present on ML410 platforms to support an external video monitor. The VGA circuitry utilizes a 140 MHz, 24-bit color video DAC (Analog Devices ADV7125KST140). DAC. Note: ...
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R PCI Express ML410 platforms that are equipped with PCI Express host connectors (P53 and P54) are capable of supporting PCI Express cores. Power distribution is handled by a MIC2959B dual-slot PCI Express hot-plug controller system protection and fault isolation. ...
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Chapter 2: ML410 Embedded Development Platform Table 2-22 Express connectors. Table 2-22: Connections from FPGA to PCI Express Slot A Net Name RXPPADA_103 RXNPADA_103 RXPPADB_103 RXNPADB_103 TXPPADA_103 TXNPADA_103 TXPPADB_103 TXNPADB_103 RXPPADA_105 RXNPADA_105 RXPPADB_105 RXNPADB_105 TXPPADA_105 TXNPADA_105 TXPPADB_105 TXNPADB_105 PCIE_SLOTA_PRSNT2# PCIE_SLOTA_PWRGD# ...
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R Table 2-23: Connections from FPGA to PCI Express Slot B Net Name RXPPADA_101 RXNPADA_101 RXPPADB_101 RXNPADB_101 TXPPADA_101 TXNPADA_101 TXPPADB_101 TXNPADB_101 RXPPADA_102 RXNPADA_102 RXPPADB_114 RXNPADB_114 TXPPADA_102 TXNPADA_102 TXPPADB_114 TXNPADB_114 PCIE_SLOTB_PRSNT2# PCIE_SLOTB_PWRGD# PCIE_SLOTB_WAKE# PCI Bus ML410 platforms provide the FPGA with ...
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Chapter 2: ML410 Embedded Development Platform generates all PCI clocks, the downstream PCI devices have no clock input prior to or during FPGA configuration; therefore, PCI Reset should be deasserted after the PCI CLK has stabilized. Please review the PCI ...
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R Table 2-24 Table 2-24: PCI Controller Connections UCF Signal Name PCI_CLK0 PCI_CLK1 PCI_CLK3 PCI_CLK4 PCI_CLK5 PCI_CLK5_FB PCI_INTA_N PCI_INTB_N PCI_INTC_N PCI_INTD_N PCI_REQ0_N PCI_REQ1_N PCI_REQ2_N PCI_REQ3_N PCI_REQ4_N PCI_GNT0_N PCI_GNT1_N PCI_GNT2_N PCI_GNT3_N PCI_GNT4_N PCI_CBE[0] PCI_CBE[1] PCI_CBE[2] PCI_CBE[3] PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_STOP_N PCI_DEVSEL_N ...
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Chapter 2: ML410 Embedded Development Platform Table 2-24: PCI Controller Connections (Cont’d) UCF Signal Name PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] ...
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R Table 2-25 along with information for each device. Table 2-25: 3.3V Primary PCI Bus Information Device Name Dev. ID Vend. ID Bus DEV IDSEL REQ PCI Slot 5 N/A N/A PCI Slot 3 N/A N/A U15, ALi SB 0x1533 ...
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Chapter 2: ML410 Embedded Development Platform ALi South Bridge Interface, M1535D+ (U15) The ALi M1535D+ South Bridge Super I/O controller with many of the basic features found on legacy PCs. These basic PC features are only accessible over the PCI ...
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R Parallel Port Interface Connector Assembly (P1) The parallel port interface of the ALi South Bridge is connected to a 25-pin connector, female DB25, which is part of the P1 connector assembly. The ALi M1535D+ supports various parallel port modes ...
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Chapter 2: ML410 Embedded Development Platform Table 2-28 Table 2-28: ALi South Bridge Connections to USB Type-A Signal Name USB_VCC USB0_DN/USB1_DN USB0_DP/USB1_DP GND IDE Connectors (J15 and J16) Supports a two-channel UltraDMA-133 IDE master controller independently connected to a primary ...
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R Table 2-29: ALi South Bridge IDE Connections (Cont’d) IDE Primary Pin (J16 ML410 Embedded Development Platform UG085 (v1.7.2) December 11, ...
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Chapter 2: ML410 Embedded Development Platform GPIO Connector (J5) There are 15 GPIO pins connecting the ALi M1535D+ to the 24-pin GPIO header (J5). These can be accessed through the ALi M1535D+ by way of the PCI bus. types and ...
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R AC’97 Audio Interface The ALi South Bridge Super I/O controller has a built-in audio interface that is combined with a standard audio codec (AC’97), LM4550. Available features include: ♦ AC’97 Codec 2.1 Specification compliant ♦ Codec variable sample rate ...
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Chapter 2: ML410 Embedded Development Platform PS/2 Keyboard and Mouse Interface Connector (P2) The ALi M1535D+ has a built-in PS2/AT keyboard and PS/2 mouse controller. The PS/2 keyboard and mouse ports are connected to the ALi M1535D+ through standard DIN ...
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R Table 2-34: ALi M1535D+ Flash Memory Interface (Cont’d) Schematic Net Name ROM_A14 ROM_A13 ROM_A12 ROM_A11 ROM_A10 ROM_A9 ROM_A8 ROM_A7 ROM_A6 ROM_A5 ROM_A4 ROM_A3 ROM_A2 ROM_A1 ROM_A0 IIC/SMBus Interface Introduction to IIC/SMBus The Inter Integrated Circuit (IIC) bus provides the ...
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Chapter 2: ML410 Embedded Development Platform IIC/SMBus on ML410 Platforms Table 2-35 platforms. These devices include EEPROM, temperature sensors, power monitors, and a Real Time Clock. Table 2-35: IIC and SMBus Controller Connections fpga_scl fpga_sda iic_irq_n iic_therm_n Notes: 1. This ...
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R FPGA (U37) ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 U27 IIC Bus SMBus Accelerator ALi South Bridge LTC1694 (U15) U20 PCI Bus Voltage Temp M1535 D+ Monitor ADDR: 0x5C LM87 U22 Real Time Clock ADDR: 0xA2 RTC8566 ...
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Chapter 2: ML410 Embedded Development Platform Table 2-36 Table 2-36: IIC Devices and Addresses Device LTC1694 RTC8564 24LC64 LM87 MIC2592B DDR2_DIMM Header Notes: 1. The IIC bus can be controlled directly by the FPGA or indirectly by the ALi bridge ...
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R SPI Addressing The SPI does not use an addressed-based system like the IIC bus interface uses. Instead, devices are selected by dedicated Slave Select signals, comparable to a Chip Select signal. Each SPI slave device needs its own Slave ...
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Chapter 2: ML410 Embedded Development Platform capacitors and resistors to AC-couple the signals. These connections are also shown in Table 2-38. Table 2-38: Connections Between FPGA and Serial ATA Connector (J25 and J26) Signal Name RXNPADA RXPPADA TXNPADA TXPPADA RXNPADB ...
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R pulse. The active-Low output of the LTC1326 pin drives the FPGA_CPU_RESET_N signal connected the FPGA. In addition to resetting the CPU, SW2 can also perform a System ACE CF reset as described in “System ACE Reset ...
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Chapter 2: ML410 Embedded Development Platform CFGADDR[2:0] = MGT Clock Source Select (SW6) SW6 is a three-position DIP switch that controls the select lines of the clock multiplexer at U6, as shown in associated SEL0 and SEL1 bits are set ...
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R Table 2-40 Table 2-40: Outputs of the Clock Multiplexer (U6) CLK_SEL0 CLK_SEL1 Front Panel Interface (J23) The front panel interface connector (J23 24-pin header that accepts a standard IDC 24 pin connector (0.1 ...
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Chapter 2: ML410 Embedded Development Platform Table 2-41 Table 2-41: Front Panel Interface Connector (J23) J23 Pin 1 SYACE_CFGA0 2 FPGA_LED_USER1 3 SYACE_CFGA1 4 FPGA_LED_USER2 5 SYACE_CFGA2 LED_DONE_R 8 GND 9 ATX_PWRLED 10 ATX_SPKR 11 SCL 12 ...
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R Jumpers Note: Pins should only be jumpered with the board powered off. 5V Fan (J8) Table 2-42 Table 2-42: 5V Fan BERG Header Connections J8 Pin 1 +5V 2 Ground Power Supply On (J19) Jumper J19 selects the power ...
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Chapter 2: ML410 Embedded Development Platform I/O Voltage Margining (J24, J29, and J37) The voltage margins on the board can be adjusted by shorting the jumpers as shown in Table 2-43. Apply shorting jumpers only when the board is powered ...
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R The different logic devices used on the ML410 platforms require a variety of voltages. Voltage levels are derived from the 5V supply and regulated on the board as shown in Figure 2-22. VCC5V VCC12V_P ATX (J18) Pin 1 3.3-A ...
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Chapter 2: ML410 Embedded Development Platform Voltage monitors connected to power indicator LEDs monitor the regulated power on the board (see out of spec, and illuminate green if the regulated supply voltage is nominal. Each regulated supply voltage has a ...
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R Table 2-44 Table 2-44: Voltage Monitor Information Schematic Net Name VCC1V2 VCC1V8 VCC2V5 VCC3_PCI VCC3V3 VCC5V VTT_DDR2 VTTDDR AVCCAUXMGT VCC12V_P VCC12V_N Notes: 1. Green LED = Voltage Nominal; Red LED = Voltage Fault ML410 Embedded Development Platform UG085 (v1.7.2) ...
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Chapter 2: ML410 Embedded Development Platform High-Speed I/O The ML410 platform’s high-speed I/O is based on the RocketIO transceiver and LVDS capability of Virtex-4 FX FPGAs. Although revision E platforms provide access to the RocketIO MGTs, the ML410 series is ...
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R Personality Module Connectors Figure 2-25 Each signal pair on the PM1 and PM2 host board connectors has a wide ground pin on the opposite side of the plastic divider, as shown in side to side along the length of ...
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Chapter 2: ML410 Embedded Development Platform All signals with length matching requirements, MGT and LVDS pairs, must include an offset to account for the Z-Dok+ propagation delays. The ML410 platforms account for one-half of the offset, while a user-designed adapter ...
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R Z-DOK+ Utility Pins Figure 2-28 connector. 6 ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 Copper Pins Figure 2-27: Adapter Board Connector Pin Detail shows the Z-DOK+ utility pins and numbering for the host board ...
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Chapter 2: ML410 Embedded Development Platform Figure 2-29 connector. Note: The pins on the adapter board connector are at varying heights, as shown in Table 2-48, page Contact Order The Z-Dok+ power and ground pins contact in the following order: ...
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R PM User I/O Pins PM1 User I/O The PM1 connector makes the MGT signals from the eight RocketIO transceivers available to the user, along with LVDS pairs and single-ended signals. for the PM1 connector. Table 2-48: PM1 Pinout FPGA ...
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Chapter 2: ML410 Embedded Development Platform Table 2-48: PM1 Pinout (Cont’d) FPGA PM1 Pin Pin Description Pin (U37) C8 AG8 IO_L27P_12 C9 AF15 IO_L17P_8 C10 AG15 IO_L17N_8 C11 AB5 IO_L7N_12 C12 AC5 IO_L7P_12 C13 A7 RXPPADA_113 C14 A6 RXNPADA_113 C15 ...
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R Table 2-48: PM1 Pinout (Cont’d) FPGA PM1 Pin Pin Description Pin (U37) D19 AP15 RXNPADB_109 D20 AP14 RXPPADB_109 F1 AB13 IO_L3P_8 F2 AA13 IO_L3N_8 F3 Y3 IO_L6N_12 F4 Y4 IO_L6P_12 _VREF _12 F5 W6 IO_L4N F6 W7 IO_L4P_12 F7 ...
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Chapter 2: ML410 Embedded Development Platform Table 2-49: PM2 Pinout (Cont’d) FPGA PM2 Pin Pin Description Pin (U37) A3 AM12 IO_L30N_8 A4 AM13 IO_L30P_8 A5 AH9 IO_L14N_8 A6 AJ9 IO_L14P_8 A7 AL23 IO_L14N_7 A8 AM23 IO_L14P_7 A9 AM11 IO_L22N_8 A10 ...
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R Table 2-49: PM2 Pinout (Cont’d) FPGA PM2 Pin Pin Description Pin (U37) A3 AM12 IO_L30N_8 A4 AM13 IO_L30P_8 A5 AH9 IO_L14N_8 A6 AJ9 IO_L14P_8 A7 AL23 IO_L14N_7 A8 AM23 IO_L14P_7 A9 AM11 IO_L22N_8 A10 AL11 IO_L22P_8 A11 AD11 IO_L11P_8 ...
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Chapter 2: ML410 Embedded Development Platform Table 2-49: PM2 Pinout (Cont’d) FPGA PM2 Pin Pin Description Pin (U37) C11 AE22 IO_L12P_7 _VREF _7 C12 AD22 IO_L12N C13 AL26 IO_L30P_SM3_7 C14 AM26 IO_L30N_SM3_7 C15 AE27 IO_L21P_7 C16 AE26 IO_L21N_7 C17 AM30 ...
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R Table 2-49: PM2 Pinout (Cont’d) FPGA PM2 Pin Pin Description Pin (U37) D19 AE28 IO_L19P_7 D20 AF28 IO_L19N_7 _SM4 _7 F1 AH25 IO_L29N F2 AG25 IO_L29P _SM4 _7 F3 AL13 IO_L32N_8 F4 AK13 IO_L32P_8 F5 AK24 IO_L22N_7 F6 AL24 ...
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Chapter 2: ML410 Embedded Development Platform 96 www.xilinx.com ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 R ...
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R Board Revisions This appendix describes the major differences in revisions of the ML410 platform. Table A-1 shows the features unique to each ML410 platform. Table A-1: Platforms, Devices, and Features Board Rev. C ML410- Feature P Virtex-4 FX FPGA ...
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The MGT and SATA clock generation and distribution for earlier board revisions (Figure A-1) differs from revision E X6 100 MHz (OSC in Socket) X10 Empty Socket X8 33 MHz OE J17 J36 U48 CLK100_Q0 CLK100_NQ0 X5 100 MHz 25 ...
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R Table A-2 describes the MGT and SATA clock connections for earlier board revisions. Table A-2: MGT and SATA Clock Connections for Revisions C and D Schematic Net Name SGMIICLK_Q0 SGMIICLK_NQ0 MGTCLK_P_110 MGTCLK_N_110 SATACLK_Q0 SATACLK_NQ0 Notes: 5. These clocks are ...
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ML410 Embedded Development Platform UG085 (v1.7.2) December 11, 2008 R ...
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R References 1. UG018, PowerPC 405 Processor Block Reference Guide 2. Processor IP User Guide www.xilinx.com/ise/embedded/proc_ip_ref_guide.pdf 3. DS302, Virtex-4 Data Sheet 4. UG076, Virtex-4 RocketIO Transceiver User Guide 5. DS080, System ACE CompactFlash Solution. 6. UG070, Virtex-4 User Guide 7. ...