R0E0200F1EMU00 Renesas Electronics America, R0E0200F1EMU00 Datasheet - Page 60

• Manufacturer Part Number: R0E0200F1EMU00
• Description: DEV EMULATOR E200 MAIN BODY
• Manufacturer: Renesas Electronics America
• Series: SuperH®r
• Type: In-Circuit Emulatorr

Specifications of R0E0200F1EMU00

• Contents: Emulator Board, Cables, Software and Documentation
• For Use With/related Products: SH7080
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.2.4
7. The AUD trace is disabled while the profiling function is used.
8. If breaks occur immediately after executing non-delayed branch and TRAPA instructions and
9. The value of [Data] is not appropriate in the trace result by the software trace (that value is
1. Set the JTAG clock (TCK) frequency to less than the frequency of the SH7286, SH7285, and
2. The initial value of the JTAG clock (TCK) is 5 MHz.
3. A value to be set for the JTAG clock (TCK) is initialized after executing [Reset CPU] or
4. When debugging is performed without connecting the EV-chip unit, set the AUD clock
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.
3. During step operation, the specified BREAKPOINT and Event Condition breaks are disabled.
4. When execution resumes from the address where a BREAKPOINT is specified and a break
5. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
Rev. 4.00 Feb. 18, 2009 Page 52 of 64
REJ10J1662-0400
3.2.3
SH7243 peripheral module clock (CKP) and 25 MHz or lower.
[Reset Go]. Thus the TCK value will be 5 MHz.
(AUDCK) frequency to 25 MHz or lower. When debugging is performed with the EV-chip
unit connected, set the AUD clock (AUDCK) frequency to 50 MHz or lower. If the higher
frequency is input, the emulator will not operate normally.
It cannot be set to the following addresses:
⎯ An area other than CS and the internal RAM
⎯ An instruction in which Event Condition 2 is satisfied
⎯ A slot instruction of a delayed branch instruction
occurs before the Event Condition execution, single-step operation is performed at the address
before execution resumes. Therefore, realtime operation cannot be performed.
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
generating a branch due to exception or interrupt, a trace for one branch will not be acquired
immediately before such breaks.
However, this does not affect on generation of breaks caused by a BREAKPOINT and a break
before executing instructions of Event Condition.
appropriate in the window trace result.).
Notes on Using the JTAG (H-UDI) Clock (TCK) and AUD Clock (AUDCK)
Notes on Setting the [Breakpoint] Dialog Box