PIC12F675/ICD Microchip Technology, PIC12F675/ICD Datasheet - Page 6

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PIC12F675/ICD

Manufacturer Part Number
PIC12F675/ICD
Description
IC MCU 1K FLASH DEVLP TOOL 14DIP
Manufacturer
Microchip Technology

Specifications of PIC12F675/ICD

Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
PIC12F629/675/PIC16F630/676
2.3.1.1
After receiving this command, the Program Counter
(PC) will be set to 0x2000. Then, by applying 16 cycles
to the clock pin, the chip will load 14 bits in a data word,
as described above, which will be programmed into the
configuration memory. A description of the memory
mapping schemes of the program memory for normal
operation and Configuration mode operation is shown in
Figure 2-3. After the configuration memory is entered,
the only way to get back to the user program memory is
to exit the Program/Verify mode by taking MCLR low
(V
FIGURE 2-3:
2.3.1.2
After receiving this command, the chip will load in a
14-bit data word when 16 cycles are applied, as
described previously. A timing diagram for the Load
Data command is shown in Figure 2-4.
FIGURE 2-4:
DS41191D-page 6
CLOCK
CLOCK
GP0
GP1
IL
GP0
GP1
DATA
DATA
).
Note 1: GP0 and GP1 apply to PIC12F629/675 only. For PIC16F630/676, use RA0 and RA1, respectively.
Note 1: GP0 and GP1 apply to PIC12F629/675 only. For PIC16F630/676, use RA0 and RA1, respectively.
(1)
(1)
(1)
(1)
Load Configuration
Load Data For Program Memory
1
1
0
0
LOAD CONFIGURATION COMMAND
LOAD DATA FOR PROGRAM MEMORY COMMAND
2
2
0
0
0
1
T
SET
3
T
0
3
0
HLD
1
1
4
4
0
0
5
x
5
x
T
T
DLY
6
DLY
6
x
x
T
T
1
DLY
1
DLY
2
2
1
strt_bit
1
strt_bit
2
2
LSb
LSb
T
3
T
3
SET
SET
T
T
HLD
HLD
1
1
1
4
1
4
© 2005 Microchip Technology Inc.
5
5
15
15
MSb
MSb
16
16
stp_bit
stp_bit

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