PIC12F675/ICD Microchip Technology, PIC12F675/ICD Datasheet - Page 8

no-image

PIC12F675/ICD

Manufacturer Part Number
PIC12F675/ICD
Description
IC MCU 1K FLASH DEVLP TOOL 14DIP
Manufacturer
Microchip Technology

Specifications of PIC12F675/ICD

Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
PIC12F629/675/PIC16F630/676
2.3.1.5
After receiving this command, the chip will transmit data
bits out of the data memory starting with the second
rising edge of the clock input. The data pin will go into
Output mode on the second rising edge and revert to
Input mode (high-impedance) after the 16th rising edge.
As previously stated, the data memory is 8 bits wide and
therefore, only the first 8 bits that are output are actual
data. If the data memory is code-protected, the data is
read as all zeros. A timing diagram of this command is
shown in Figure 2-7.
FIGURE 2-7:
2.3.1.6
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 2-8.
It is not possible to decrement the address counter. To
reset this counter, the user should exit and re-enter
Programming mode.
FIGURE 2-8:
DS41191D-page 8
CLOCK
GP0
GP1
DATA
CLOCK
GP0
GP1
DATA
Note 1: GP0 and GP1 apply to PIC12F629/675 only. For PIC16F630/676, use RA0 and RA1, respectively.
Note 1: GP0 and GP1 apply to PIC12F629/675 only. For PIC16F630/676, use RA0 and RA1, respectively.
(1)
(1)
(1)
(1)
Read Data From Data Memory
T
Increment Address
SET
1
1
1
READ DATA FROM DATA MEMORY COMMAND
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
2
0
1
0
T
HLD
3
1
1
Input
2
1
4
0
T
3
1
SET
5
x
1
x
6
4
T
0
T
DLY
DLY
2
1
T
strt_bit
1
HLD
5
x
1
2
LSb
x
6
T
DLY
T
3
T
DLY
DLY
3
2
1
4
1
Output
x
© 2005 Microchip Technology Inc.
Next Command
5
2
0
15
MSb
16
Input
stp_bit

Related parts for PIC12F675/ICD