PIC12F675/ICD Microchip Technology, PIC12F675/ICD Datasheet - Page 17
PIC12F675/ICD
Manufacturer Part Number
PIC12F675/ICD
Description
IC MCU 1K FLASH DEVLP TOOL 14DIP
Manufacturer
Microchip Technology
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
Specifications of PIC12F675/ICD
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2.2.2.5
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-4
bit 3
bit 2-1
bit 0
R/W-0
EEIF
PIR1 Register
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only)
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
Unimplemented: Read as ‘0’
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1: PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
CMIF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
PIC12F629/675
U-0
—
x = Bit is unknown
U-0
—
DS41190G-page 17
TMR1IF
R/W-0
bit 0
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