PIC12F675/ICD Microchip Technology, PIC12F675/ICD Datasheet - Page 22
PIC12F675/ICD
Manufacturer Part Number
PIC12F675/ICD
Description
IC MCU 1K FLASH DEVLP TOOL 14DIP
Manufacturer
Microchip Technology
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
Specifications of PIC12F675/ICD
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PIC12F629/675
REGISTER 3-2:
REGISTER 3-3:
DS41190G-page 22
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3
bit 2-0
Note 1:
Note:
U-0
U-0
—
—
2:
Global GPPU must be enabled for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).
TRISIO<3> always reads ‘1’.
Unimplemented: Read as ‘0’
TRISIO<5:0>: General Purpose I/O Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
Unimplemented: Read as ‘0’
WPU<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPU<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
U-0
U-0
—
—
TRISIO: GPIO TRI-STATE REGISTER (ADDRESS: 85h)
WPU: WEAK PULL-UP REGISTER (ADDRESS: 95h)
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
TRISIO5
WPU5
R/W-1
R/W-1
TRISIO4
R/W-1
R/W-1
WPU4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRISIO3
R-1
U-0
—
TRISIO2
R/W-1
R/W-1
WPU2
2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
TRISIO1
WPU1
R/W-1
R/W-1
TRISIO0
R/W-1
R/W-1
WPU0
bit 0
bit 0
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