AD8347-EVAL Analog Devices Inc, AD8347-EVAL Datasheet - Page 22

• Manufacturer Part Number: AD8347-EVAL
• Description: BOARD EVAL FOR AD8347
• Manufacturer: Analog Devices Inc

Specifications of AD8347-EVAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD8347
If the VGA is operating in AGC mode, the detector inputs
(VDT1 and VDT2) can be tied either to the inputs or outputs of
the filter. Connecting the detector inputs to the inputs of the
filter (IMXO and QMXO) causes the VGA leveling point to be
determined by the composite of the wanted signal and any
unfiltered components, such as blockers or signal harmonics.
Alternatively, connecting VDT1 and VDT2 to the outputs of the
filters ensures that the leveling point of the AGC circuit is based
upon the amplitude of the filtered output only. The latter option
is more desirable as it results in a more constant baseband
output. However, when using this method, set the leveling point
of the AGC so that the out-of-band blockers do not overdrive
the mixer output.
50
45
40
35
30
25
20
15
10
Figure 52. Group Delay of 20 MHz Baseband Low-Pass Filter
0
5
1
FREQUENCY (MHz)
10
100
Rev. A | Page 22 of 28
DC OFFSET COMPENSATION
Feedthrough of the LO signal to the RF input port results in
self-mixing of the LO signal. This produces a dc component at
the mixer output that is frequency dependent.
The AD8347 includes an internal circuit that actively nulls any
dc offsets that appear at the mixer output. The dc bias level of
the mixer output (which should ideally equal V
level for the baseband sections of the chip) is continually com-
pared to V
and V
The time constant of this correction loop is set by the capacitors
that are connected to Pin IOFS and Pin QOFS (each output can
be separately compensated). For normal operation, 0.1 μF
capacitors are recommended. The corner frequency of the
compensation loop is given approximately by
The corner frequency must be set to a frequency that is much
lower than the symbol rate of the demodulated data. This
prevents the compensation loop from falsely interpreting the
data stream as a changing offset voltage.
To disable the offset compensation circuits, tie IOFS and QOFS
to VREF.
f
VREF
3
dB
forces a compensating voltage on to the mixer output.
VREF
=
C
. Any differences between the mixer output level
40
OFS
(
C
OFS
in
μF
)
VREF
, the bias