AD9866-EB Analog Devices Inc, AD9866-EB Datasheet - Page 28

• Manufacturer Part Number: AD9866-EB
• Description: BOARD EVAL FOR AD9866
• Manufacturer: Analog Devices Inc

Specifications of AD9866-EB

• Rohs Status: RoHS non-compliant

AD9866
TRANSMIT PATH
The AD9866 (or AD9865) transmit path consists of a selectable
digital 2×/4× interpolation filter, a 12-bit (or 10-bit) TxDAC,
and a current-output amplifier (IAMP), as shown in Figure 59.
Note that the additional two bits of resolution offered by the
AD9866 (vs. the AD9865) result in a 10 dB to 12 dB reduction
in the pass-band noise floor. The digital interpolation filter
relaxes the Tx analog filtering requirements by simultaneously
reducing the images from the DAC reconstruction process
while increasing the analog filter’s transition band. The digital
interpolation filter can also be bypassed, resulting in lower
digital current consumption.
ADIO[11:6]/
DIGITAL INTERPOLATION FILTERS
The input data from the Tx port can be fed into a selectable
2×/4× interpolation filter or directly into the TxDAC (for a half-
duplex only). The interpolation factor for the digital filter is set
via SPI Register 0x0C with the settings shown in Table 18. The
maximum input word rate, f
80 MSPS; the maximum DAC update rate is 200 MSPS. There-
fore, applications with input word rates at or below 50 MSPS
can benefit from 4× interpolation, while applications with input
word rates between 50 MSPS and 80 MSPS can benefit from
2× interpolation.
Table 18. Interpolation Factor Set via SPI Register 0x0C
Bits [7:6]
00
01
10
11
The interpolation filter consists of two cascaded half-band filter
stages with each stage providing 2× interpolation. The first
stage filter consists of 43 taps. The second stage filter, operating
at the higher data rate, consists of 11 taps. The normalized wide
band and pass-band filter responses (relative f
and 4× low-pass interpolation filters are shown in Figure 60 and
Figure 61, respectively. These responses also include the
inherent sinc(x) from the TxDAC reconstruction process and
can be used to estimate any post analog filtering requirements.
ADIO[11:6]/
TXEN/SYNC
Rx[5:0]
Tx[5:0]
TXCLK
Figure 59. Functional Block Diagram of Tx Path
10
Interpolation Factor
4
2
1 (half-duplex only)
Do not use
2-4X
AD9865/AD9866
DATA
, into the interpolation filter is
TxDAC
0 TO –7.5dB
DATA
0 TO –12dB
IAMP
) for the 2×
IOUT_G+
IOUT_N+
IOUT_N–
IOUT_G–
Rev. A | Page 28 of 48
The pipeline delays of the 2× and 4× filter responses are 21.5
and 24 clock cycles, respectively, relative to f
is also taken into consideration for applications configured for a
half-duplex interface with the half-duplex power-down mode
enabled. This feature allows the user to set a programmable
delay that powers down the TxDAC and IAMP only after the
last Tx input sample has propagated through the digital filter.
See the Power Control and Dissipation section for more details.
TxDAC AND IAMP ARCHITECTURE
The Tx path contains a TxDAC with a current amplifier, IAMP.
The TxDAC reconstructs the output of the interpolation filter
and sources a differential current output that can be directed to
an external load or fed into the IAMP for further amplification.
The TxDAC’s and IAMPS’s peak current outputs are digitally
programmable over a 0 to −7.5 dB and 0 to −19.5 dB range,
respectively, in 0.5 dB increments. Note that this assumes
default register settings for Register 0x10 and Register 0x11.
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
10
0
0
0
0
PASS BAND
Figure 60. Frequency Response of 2× Interpolation Filter
Figure 61. Frequency Response of 4× Interpolation Filter
WIDE BAND
WIDE BAND
0.25
0.5
NORMALIZED FREQUENCY (Relative to
NORMALIZED FREQUENCY (Relative to
PASS BAND
–1.0dB @ 0.45
0.50
1.0
–1.0dB @ 0.441
(Normalized to f
(Normalized to f
0.75
1.5
f
DATA
1.00
2.0
f
1.25
DATA
2.5
DATA
DATA
)
)
1.50
3.0
f
f
DATA
DATA
DATA
1.75
. The filter delay
)
3.5
)
2.00
4.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5