AD9876-EB Analog Devices Inc, AD9876-EB Datasheet - Page 20

• Manufacturer Part Number: AD9876-EB
• Description: BOARD EVAL FOR AD9876
• Manufacturer: Analog Devices Inc

Specifications of AD9876-EB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD9876

AD9876
the first address to be accessed. The AD9876 will automatically
increment the address for each successive byte required for the
multibyte communication cycle.
Figures 10a and 10b show how the serial port words are built
for each of these modes.
SENABLE
Address
(hex)
0
1
2
3
4
5
6
7
8
F
SENABLE
SDATA
Figure 10a. Serial Register Interface Timing MSB-First
SCLK
Figure 10b. Serial Register Interface Timing LSB-First
SDATA
SCLK
R/W I6
Bit 7
Power-
Down
Regulator
Power-
Down
Regulator
Tx Port
Negative
Edge
Sampling
Rx Port
Negative
Edge
Sampling
Invert
CLK-B
I0
INSTRUCTION CYCLE
(N)
I1
INSTRUCTION CYCLE
I5
(N)
I2
I4
I3
I3
Bit 6
SPI
LSB First
Power-
Down
PLL-B
Power-
Down
PLL-B
ADC Clock
Source
PLL-B/2
Rx LPF
Tuning
In Progress
(Read-Only)
Interpolation Filter Select
<3:0>
Invert
CLK-A
I4
I2
I5
(N)
I1
I6
(N)
I0
R/W
D7
N
D0
D6
Bit 5
Software
Reset
Power-
Down
PLL-A
Power-
Down
PLL-A
Rx Path
DC Offset HPF
Correction Bypass
PGA
Gain Set
by Register
Disable
CLK-B
DATA TRANSFER CYCLE
0
N
D1
DATA TRANSFER CYCLE
0
D2
(×M) Multiplier
<5:4>
PLL-B
Rx LPF f
0
Bit 4
Power-
Down
DAC
Power-
Down
DAC
Rx Digital Fast ADC
Disable
CLK-A
D2
0
c
D1
Table IV. Register Layout
Adjust <7:0>
D6
0
N
D0
D7
0
N
Bit 3
Power-
Down
Interpolator
Power-
Down
Interpolator
Sampling
Power-Down Tx Port
Interpolator
at
Tx QUIET
Pin Low
Three-State
Rx Port
Rx Path Gain Adjust <4:0>
–20–
Die Revision Number <3:0>
PLL-B
( N) Divider
<3:3>
Notes on Serial Port Operation
The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all
registers except Register 0 are set to their default values. Regis-
ter 0 will remain at the last value sent, with the exception that
the Software Reset Bit will be set to 0.
The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK, a
byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9876 are not simultaneously
updated but occur sequentially. For this reason, it is recom-
mended that single byte transfers be used when changing the
SPI configuration or performing a software reset.
Bit 2
Power-
Down
Rx
Reference
Power-
Down
Rx
Reference
Wideband
Rx LPF
LS Nibble
First
Rx Port
LS Nibble
First
Bit 1
Power-
Down
ADC and Rx LPF and
FPGA
Power-
Down
ADC and Rx LPF and
FPGA
Enable
1-Pole
Rx LPF
PLL-A
(×M) Multiplier
<1:0>
Bit 0
Power-
Down
CPGA
Power-
Down
CPGA
Rx LPF
Bypass
Tx Port
Demultiplexer
Bypass
Rx Port
Multiplexer
Bypass
Default
(hex)
0 × 00
0 × 00
0 × 9F
0 × 02
0 × 01
0 × 80
0 × 00
0 × 00
0 × 00
Comments
Read/Write
Read/Write
PWR DN
Pin Low
Read/Write
PWR DN
Pin High
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read- Only
REV. A