EVAL-AD1835EB Analog Devices Inc, EVAL-AD1835EB Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD1835EB
• Description: BOARD EVAL FOR AD1835
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1835EB

• Rohs Status: RoHS non-compliant

AD1835
Pin Name
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
DSDATA4 (I)/AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
DLRCLK (I)/AUXLRCLK(I/O)
DBCLK (I)/AUXBCLK(I/O)
(FROM AUX ADC 1)
(FROM AUX ADC 1)
(FROM AUX ADC 1)
(FROM AUX ADC 2)
(FROM AUX ADC 3)
AAUXDATA1 (IN)
AAUXDATA2 (IN)
AAUXDATA3 (IN)
TDM (OUT)
LRCLK I
DSDATA1
ASDATA1
DSDATA1
BCLK I
TDM (IN)
ASDATA
FSTDM
BCLK
TDM
AUX
AUX
2
2
S
S
AUX BCLK FREQUENCY IS 64
MSB TDM
MSB TDM
1ST
1ST
CH
CH
INTERNAL
INTERNAL
ADC L1
DAC L1
32
32
I
I
I
I
I
I
LRCLK for ADC
BCLK for ADC
LRCLK In/Out Internal DACs
BCLK In/Out Internal DACs
2
2
2
2
2
2
S Mode
S Data Out, Internal ADC
S Data In, Internal DAC1
S Data In, Internal DAC2
S Data In, Internal DAC3
S Data In, Internal DAC4
Table II. Pin Function Changes in Auxiliary Mode
AUX_ADC L2
INTERNAL
DAC L2
I
I
I
2
2
2
S—MSB LEFT
S—MSB LEFT
S—MSB LEFT
FRAME-RATE; TDM BCLK FREQUENCY IS 256
Figure 11. Aux Mode Timing
LEFT
AUX_ADC L3
INTERNAL
DAC L3
–16–
AUX_ADC L4
INTERNAL
DAC L4
Aux Mode
TDM Data Out to SHARC
TDM Data In from SHARC
AUX-I
AUX-I
AUX-I
TDM Frame Sync Out to SHARC (FSTDM)
TDM BCLK Out to SHARC
AUX LRCLK In/Out. Driven by Ext. LRCLK from ADC in
slave mode. In master mode, driven by MCLK/512.
AUX BCLK In/Out. Driven by Ext. BCLK from ADC
in slave mode. In master mode, driven by MCLK/8.
INTERNAL
INTERNAL
ADC R1
DAC R1
2
2
2
S Data In 1 (from Ext. ADC)
S Data In 2 (from Ext. ADC)
S Data In 3 (from Ext. ADC)
FRAME-RATE.
AUX_ADC R2
INTERNAL
DAC R2
AUX_ADC R3
INTERNAL
DAC R3
RIGHT
I
I
I
2
2
2
S—MSB RIGHT
S—MSB RIGHT
S—MSB RIGHT
AUX_ADC R4
INTERNAL
MSB TDM
MSB TDM
DAC R4
8TH
8TH
CH
CH
REV. B