AD9956-VCO/PCB Analog Devices Inc, AD9956-VCO/PCB Datasheet - Page 6

• Manufacturer Part Number: AD9956-VCO/PCB
• Description: BOARD EVAL 14BIT 1.8V 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9956-VCO/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD9956
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9956/PCB
Select Clear Frequency Accum. or Clear Phase Accum. to
clear and hold the corresponding accumulator. The clear
function clears and then holds the contents of the correspond-
ing accumulator to 0 until you uncheck the box.
Sync Multi DUTs
This section controls the multiple synchronization functions of
the AD9956.
Select Auto Sync and then click LOAD to turn on the auto-
synchronization routine of the DDS. When this function is on,
the DDS aligns its internal DDS clock edge to a sync signal,
supplied on the PLL_LOCK/SYNC_IN pin. Once the clock
edge is aligned, this function should be turned off because it
does not provide continuous monitoring.
Select Software Manual Sync to advance the SYNC-CLK rising
edge by one system clock period. Once executed, the bit is
cleared. To advance multiple system clock periods, select this
box and then click LOAD several times.
Select Hardware Manual Sync to advance the sync clock rising
edge by one system clock period for each rising edge detected
on the SYNC_IN pin. This bit does not self-clear.
Select High Speed Sync Enable to turn on a high speed
synchronization algorithm that you can use to synchronize
multiple DDSs operating at a 250 MSPS system clock rate or
faster. Do not select this box for system clock rates below
250 MSPS.
Select Sync CLK Out Disable to turn off the sync clock output.
The PLL lock detect enable bit in the Charge Pump dialog box
enables a PLL lock monitoring function, either through the
PLL_LOCK_DETECT pin (externally) or by setting a flag in the
control register, CFR1<24>, which is the PLL lock error bit.
When you turn on auto-synchronization or hardware manual
synchronization, the PLL_LOCK/SYNC_IN pin becomes an
input, and the ability to monitor the lock detect signal
externally is lost. This flag is stored at CFR1<24> and clears
itself when the register is read, that is, the flag is seen and then
auto-cleared. If, during a readback, the evaluation software
detects that this flag is set, the PLL_LOCK_ERROR bar at the
bottom of this section flashes. The next time the flag is read, the
bar stops flashing if the flag is cleared.
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PROFILE DIALOG BOX
The DDS section of the AD9956 has eight programmable
frequency and phase offset profiles. You can write values for
these profiles in the Profile dialog box, shown in Figure 4.
To select the active profile, click the corresponding Active
Profile button (Profile 0 to Profile 7) at the bottom of the
dialog box. Changing profiles is an immediate selection; no
LOAD is required.
During linear sweep modes of operation, the Ramp Up and
Ramp Down buttons are displayed at the bottom of the Profile
dialog box, as shown in Figure 5. Click the appropriate button
to either ramp the part up to the value stored in Profile 1 or to
ramp the part down to the value stored in Profile 0.
Figure 5. Profile Dialog Box when Linear Sweep Is Enabled
Figure 4. Profile Dialog Box