AD9540-VCO/PCB Analog Devices Inc, AD9540-VCO/PCB Datasheet - Page 10

• Manufacturer Part Number: AD9540-VCO/PCB
• Description: BOARD EVAL CLK GEN SYNTH 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9540-VCO/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD9540 with VCO
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9540
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1, 3, 8, 26, 30,
34, 37, 43,
2, 4, 7, 27, 38,
44, 48
5
6
9
10
11, 25
12, 24
13
14
15
16
17
18
19
20
Mnemonic
AGND
AVDD
IOUT
IOUT
I/O_RESET
RESET
DVDD
DGND
SDO
SDI/O
SCLK
CS
DVDD_I/O
SYNC_OUT
SYNC_IN/STATUS
I/O_UPDATE
I/O_RESET
RESET
AGND
AGND
AGND
DGND
AVDD
AVDD
AVDD
DVDD
Master Reset. Clears all accumulators and returns all registers to their default values (active high).
IOUT
IOUT
Description
Analog Ground.
Analog Core Supply (1.8 V).
DAC Analog Output.
DAC Analog Complementary Output.
Resets the serial port when synchronization is lost in communications but does not reset the
device itself (active high). When not being used, this pin should be forced low, because it floats to
the threshold value.
Digital Core Supply (1.8 V).
Digital Ground.
Serial Data Output. Used only when the device is programmed for 3-wire serial data mode.
Serial Data Input/Output. When the part is programmed for 3-wire serial data mode, this is input
only; in 2-wire mode, it serves as both the input and output.
Serial Data Clock. Provides the clock signal for the serial data port.
Active Low Signal That Enables Shared Serial Buses. When brought high, the serial port ignores the
serial data clocks.
Digital Interface Supply (3.3 V).
Synchronization Clock Output.
Bidirectional Dual Function Pin. Depending on device programming, this pin is either the direct
digital synthesizer’s (DDS) synchronization input (allows alignment of multiple subclocks), or the PLL
lock detect output signal.
This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the
rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.
10
11
12
1
2
3
4
5
6
7
8
9
Figure 3. 48-Lead LFCSP Pin Configuration
PIN 1
INDICATOR
Rev. A | Page 10 of 32
(Not to Scale)
AD9540
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
CP_OUT
CP_VDD
AGND
OUT0
OUT0
CP_VDD
AGND
CLK1
CLK1
AVDD
AGND
DVDD