AD9444-LVDS/PCB Analog Devices Inc, AD9444-LVDS/PCB Datasheet - Page 11

• Manufacturer Part Number: AD9444-LVDS/PCB
• Description: BOARD EVAL 14BIT LVDS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9444-LVDS/PCB

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 1.25W @ 80MSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9444
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode
Pin No.
1, 8 to 9,
16 to 18,
24 to 27,
34 to 35, 38,
41 to 42, 87,
89 to 95, 98
2 to 4
5
6
7
10
11
12, 15, 20,
23, 32, 86,
88, 96 to 97,
99, Exposed
Heat Sink
13
14
19, 28 to 31,
39 to 40
21
22
33
36
37
43
Mnemonic
AVDD1
DNC
OUTPUT
MODE
DFS
LVDSBIAS
SENSE
VREF
AGND
REFT
REFB
AVDD2
VIN+
VIN−
C1
CLK+
CLK−
D0− (LSB)
Description
3.3 V (±5%) Analog Supply.
Do Not Connect. These pins
should float.
CMOS Compatible Output Logic
Mode Control Pin. OUTPUT MODE
= 0 for CMOS mode, and OUTPUT
MODE = 1 (AVDD1) for LVDS
outputs.
Data Format Select Pin. CMOS
control pin that determines the
format of the output data. DFS =
high (AVDD1) for twos comple-
ment, DFS = low (ground) for
offset binary format.
Set Pin for LVDS Output Current.
Place 3.7 kΩ resistor terminated to
DRGND.
Reference Mode Selection.
Connect to AGND for internal 1 V
reference, and connect to AVDD2
for external reference.
1.0 V Reference I/O—Function
Dependent on SENSE. Decouple
to ground with 0.1 µF and 10 µF
capacitors.
Analog Ground. The exposed
heat sink on the bottom of the
package must be connected to
AGND.
Differential Reference Output.
Decoupled to ground with 0.1 µF
capacitor and to REFB (Pin 14) with
0.1 µF and 10 µF capacitors.
Differential Reference Output.
Decoupled to ground with a 0.1 µF
capacitor and to REFT (Pin 13) with
0.1 µF and 10 µF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Internal Bypass Node. Connect a
0.1 µF capacitor from this pin
to AGND.
Clock Input—True.
Clock Input—Complement.
D0 Complement Output Bit
(LVDS Levels).
Rev. 0 | Page 11 of 40
Pin No.
44
45
46
47, 54, 62,
75, 83
48, 53, 61,
67, 74, 82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
100
Mnemonic
D0+
D1−
D1+
DRVDD
DRGND
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
D6−
D6+
DCO−
DCO+
D7−
D7+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
D12−
D12+
D13−
D13+ (MSB)
OR−
OR+
DCS MODE
Description
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
3.3 V Digital Output Supply
(3.0 V to 3.6 V).
Digital Ground.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output.
D13 True Output Bit.
Out-of-Range Complement
Output Bit.
Out-of-Range True Output Bit.
Clock Duty Cycle Stabilizer (DCS)
Control Pin, CMOS-Compatible.
DCS = low (AGND) to enable DCS
(recommended). DCS = high
(AVDD1) to disable DCS.
AD9444