AD9444-LVDS/PCB Analog Devices Inc, AD9444-LVDS/PCB Datasheet - Page 22

• Manufacturer Part Number: AD9444-LVDS/PCB
• Description: BOARD EVAL 14BIT LVDS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9444-LVDS/PCB

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 1.25W @ 80MSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9444
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9444
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
For that reason, considerable care was taken in the design of the
clock inputs of the AD9444, and the user is advised to give
careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to the clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic perform-
ance characteristics. The AD9444 contains a clock duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. As
shown in Figure 32, noise and distortion performance are nearly
flat for a 30% to 70% duty cycle with the DCS enabled. The DCS
circuit locks to the rising edge of CLK+ and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not re-
duced by the internal stabilization circuit. The duty cycle con-
trol loop does not function for clock rates less than 30 MHz
nominally. The loop has a time constant associated with it that
needs to be considered in applications where the clock rate can
change dynamically, which requires a wait time of 1.5 µs to 5 µs
after a dynamic clock frequency increase (or decrease) before
the DCS loop is relocked to the input signal. During the time
period the loop is not locked, the DCS loop is bypassed, and the
internal device timing is dependant on the duty cycle of the
input clock signal. In such an application, it may appropriate to
disable the duty cycle stabilizer. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabi-
lizer, and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9444 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of
performance. Maintaining 14-bit accuracy places a premium on
the encode clock phase noise. SNR performance can easily
degrade by 3 dB to 4 dB with 70 MHz analog input signals
when using a high jitter clock source. (See AN-501, Aperture
Uncertainty and ADC System Performance, for complete
details.) For optimum performance, the AD9444 must be
clocked differentially. The sample clock inputs are internally
biased to ~2.2 V, and the input signal is usually ac-coupled into
Rev. 0 | Page 22 of 40
the CLK+ and CLK− pins via a transformer or capacitors.
Figure 44 shows one preferred method for clocking the AD9444.
The clock source (low jitter) is converted from single-ended-to-
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD9444 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9444 and limits the noise
presented to the sample clock inputs.
If a low jitter clock is available, another option is to ac couple a
differential ECL/PECL signal to the encode input pins, as shown
in Figure 46.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency ( f
( t
In the equation, the rms aperture jitter represents the root-mean
square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
see Figure 46.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9444. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
J
) can be calculated using the following equation.
SNR = 20 log[2 πf
SOURCE
CLOCK
Figure 44. Crystal Clock Oscillator, Differential Encode
INPUT
PECL
ECL/
) and rms amplitude due only to aperture jitter
Figure 45. Differential ECL for Encode
0.1 µF
INPUT
ADT1–1WT
VT
VT
× t
0.1 µF
0.1µF
J
]
HSMS2812
DIODES
ENCODE
ENCODE
AD9444
CLK+
CLK–
AD9444