HSC-ADC-FPGA-4 Analog Devices Inc, HSC-ADC-FPGA-4 Datasheet - Page 2

• Manufacturer Part Number: HSC-ADC-FPGA-4
• Description: BOARD FPGA QUAD LVDS FOR ADC
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-FPGA-4

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

HSC-ADC-FPGA
TABLE OF CONTENTS
Features .............................................................................................. 1
Equipment Needed........................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
HSDB Quick Start............................................................................. 3
Deserialization Board....................................................................... 4
Theory of Operation ........................................................................ 5
REVISION HISTORY
10/06—Rev. B to Rev. C
Added Quad-/Octal-Channel High Speed Serial LVDS to
Changes to Figure 2.......................................................................... 4
Changes to Table 1............................................................................ 4
Changes to Figure 3.......................................................................... 5
Changes to Channel Selection Settings Section ........................... 6
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 6
Changes to Figure 5 to Figure 14.................................................... 8
Changes to Table 6.......................................................................... 18
Changes to Ordering Guide .......................................................... 20
Requirements ................................................................................ 3
Additional Information and Updates ........................................ 3
Quick Start Steps .......................................................................... 3
Supported ADC Evaluation Boards ........................................... 4
Code Description ......................................................................... 5
Manual Installation and Customization.................................... 5
Parallel CMOS Converter (HSC-ADC-FPGA-8) .....Universal
Rev. C | Page 2 of 20
Jumpers ...............................................................................................6
Evaluation Board ...............................................................................8
HSDB Schematics and PCB Layout ................................................9
Ordering Information.................................................................... 18
11/05—Rev. A to Rev B
Changed HSC-ADC-EVALA-DC to
Changes to Figure 1...........................................................................1
Changes to Table 1.............................................................................4
Changes to the Theory of Operation Section and Figure 3 .........5
Added the SPI Interface Section......................................................7
Changes to Figure 5...........................................................................8
Changes to Figure 6...........................................................................9
Updated Schematic and Layout to Rev D ................................9-17
Changes to Table 6.......................................................................... 17
Changes to Ordering Guide .......................................................... 20
02/05—Rev. 0 to Rev. A
Updated Bill of Materials............................................................... 15
Changes to Ordering Guide .......................................................... 16
10/04—Revision 0: Initial Version
Resolution Settings........................................................................6
Channel Selection Settings...........................................................6
Data Alignment .............................................................................6
DCO Phase Alignment.................................................................6
SPI® Interface..................................................................................7
FIFO Jumper Settings ...................................................................7
Power Supplies ...............................................................................8
Bill of Materials........................................................................... 18
Ordering Guide .......................................................................... 20
ESD Caution................................................................................ 20
HSC-ADC-EVALA/B-DC............................................Universal