Z8018100ZCO Zilog, Z8018100ZCO Datasheet - Page 69
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Z8018100ZCO
Manufacturer Part Number
Z8018100ZCO
Description
Z80181 SAC APPLICATION BOARD
Manufacturer
Zilog
Datasheet
1.Z8018110FEG.pdf
(74 pages)
Specifications of Z8018100ZCO
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Z8018100ZC0
Z8018100ZC0
Z8018100ZC0
- Current page: 69 of 74
- Download datasheet (594Kb)
Zilog
Note for Interrupt Acknowledge Cycle and
Daisy Chain
When using the interrupt daisy chained device(s) for other
than the Z181 (without external logic), the following restric-
tions/notes apply:
The device(s) must be connected to the higher priority
location (Figure 75).
The device(s) IEI-IEO delay must be less than two clock
cycles.
The Z181 on-chip interface logic inserts another three wait
states into the interrupt acknowledge cycle to meet the on-
chip SCC and the Z80 CTC timing requirements. (For a
total of five wait states, including the two automatically
inserted wait states).
To meet the timing requirements, the Z181’s on-chip circuit
generates interface signals for the SCC and CTC.
Figure 78 has the timing during the interrupt acknowledge
cycle, including the internally generated signals.
DS971800500
Vcc
IEI
Figure 75. Peripheral Device as Part of the Daisy Chain
Peripheral
Device(s)
IEO
PS009701-0301
IEI
CTC
The following are three separate cases for the daisy-chain
settle times:
Case 1 - SCC: The SCC /INTACK signal goes active on the
T1 clock fall time. The settle time is from SCC /INTACK
active until the SCC /RD signal goes active on the fourth
rising wait state clock.
Case 2 - CTC: The settle time for the on-chip /IORQ is
between the fall of /M1 until the internal CTC /IORQ goes
active on the rise of the fourth wait state (the same time as
SCC /RD goes active).
Case 3 - OFF-chip Z80 Peripheral: The settle time for the
off-chip Z80 peripheral is from the fall of /M1 until CTC
/IORQ goes active. Since the Z181’s external /IORQ signal
goes active on the clock fall of the first automatically
inserted wait state (T
must be connected to the upper chain location. Also, it
must settle within two clock cycles.
If any peripheral is connected externally with a lower daisy
chain priority than Z181 peripherals, /IORQ must be de-
layed by external logic as shown in Figure 79.
IEO
Z80181
IEI
SCC
WA
), the external daisy-chain device
IEO
S
MART
A
CCESS
C
ONTROLLER
Z80181
2-69
SAC
™
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