KS8695P-EVAL Micrel Inc, KS8695P-EVAL Datasheet - Page 17

• Manufacturer Part Number: KS8695P-EVAL
• Description: BOARD EVAL EXPERIMENT KS8695P
• Manufacturer: Micrel Inc

Specifications of KS8695P-EVAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 576-1002

System Level Hardware Interfaces
At the system level the KS8695P features the following interfaces:
• Clock interface for crystal or external oscillator
• JTAG development interface
• One WAN Ethernet physical interface
• Four LAN Ethernet physical interfaces
• PHY LED drivers
• One high-speed UART interface
• Sixteen GPIO pins
• 33MHz, 32-bit PCI interface supporting three external masters
• Advanced memory interface
• Factory test
• Power and ground
Configuration Pins
The following pins are sampled as input during reset
August 2005
KS8695P
Configuration
Bank0 Flash Data Width
WRSTO Polarity
CPU Clock Select
PCI Bridge Mode
CPUCLKSEL
Debug Enable
– Programmable synchronous bus rate
– Programmable asynchronous interface timing
– Independently programmable data bus width for static and synchronous memory
– Glueless connection to SDRAM
– Glueless connection to flash memory or ROM
Clock and Reset
WAN Ethernet
LAN Ethernet
Factory Test
PHY LED
Drivers
JTAG
PHY
PHY
Pin Name
B0SIZE[1:0]
EROEN/WRSTPLS
URTSN/CPUCLKSEL
PBMS
URTSN/CPUCLKSEL
UDTRN/DBGENN
Figure 3. System Level Interfaces
Table 1. Configuration Pins
KS8695P
17
Pin #
E14, E15
U17
M15
D3
M15
N15
Setting
‘00’= reserved
‘01’ = byte wide
‘10’ = half word wide (16 bits)
‘11’ = word wide (32 bits)
‘0’ = active high
‘1’ = active low
‘0’ = normal mode (PLL)
'1’ = bypass internal PLL
‘0’ = guest bridge mode
‘1’ = host bridge mode
‘0’ = normal operation
‘1’ = factory reserved
‘0’ = factory reserved
UART
GPIO
PCI
Advanced
Memory
Interface
Ground
Power and
M9999-081805
Micrel