KS8695P-MDP-EVAL Micrel Inc, KS8695P-MDP-EVAL Datasheet - Page 18

• Manufacturer Part Number: KS8695P-MDP-EVAL
• Description: EVAL KIT EXPERIMENTAL KS8695PMPD
• Manufacturer: Micrel Inc

Specifications of KS8695P-MDP-EVAL

• Lead Free Status / RoHS Status: Not applicable / Not applicable

Signal Description
System Level Hardware Interfaces
At the system level the KS8695P features the following interfaces:
• Clock interface for crystal or external oscillator
• JTAG development interface
• One WAN Ethernet physical interface
• Four LAN Ethernet physical interfaces
• PHY LED drivers
• One high-speed UART interface
• Sixteen GPIO pins
• 33MHz, 32-bit PCI interface supporting three external masters
• Advanced memory interface
• Factory test
• Power and ground
Configuration Pins
The following pins are sampled as input during reset.
Configuration
Bank0 Flash Data Width
WRSTO Polarity
CPU Clock Select
PCI Bridge Mode
CPUCLKSEL
Debug Enable
Micrel, Inc.
May 2006
– Programmable synchronous bus rate
– Programmable asynchronous interface timing
– Independently programmable data bus width for static and synchronous memory
– Glueless connection to SDRAM
– Glueless connection to flash memory or ROM
B0SIZE[1:0]
Pin Name
EROEN/WRSTPLS
URTSN/CPUCLKSEL
PBMS
URTSN/CPUCLKSEL
UDTRN/DBGENN
Figure 3. System Level Interfaces
Table 1. Configuration Pins
Pin #
E14, E15
U17
M15
D3
M15
N15
18
Setting
‘00’= reserved
‘01’ = byte wide
‘10’ = half word wide (16 bits)
‘11’ = word wide (32 bits)
‘0’ = active high
‘1’ = active low
‘0’ = normal mode (PLL)
'1’ = bypass internal PLL
‘0’ = guest bridge mode
‘1’ = host bridge mode
‘0’ = normal operation
‘1’ = factory reserved
‘0’ = factory reserved
M9999-051806
KS8695P