KS8993F-EVAL Micrel Inc, KS8993F-EVAL Datasheet
KS8993F-EVAL
Specifications of KS8993F-EVAL
Related parts for KS8993F-EVAL
KS8993F-EVAL Summary of contents
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... General Description The Micrel KS8993F is the industry’s first single chip Fast Ethernet Media Converter with built-in OAM functions. The KS8993F integrates three MACs, two PHYs, OAM, frame buffer and high performance switch into a single chip ideal for use in 100BASE-FX to 10BASE-T or 100BASE- TX conversion in the FTTx market ...
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... Per-port based software power-save on PHY (idle link detection, register configuration preserved) • 0.18um CMOS technology • Voltages: Core 1.8V I/O and Transceiver 3.3V • Available in 128-pin PQFP Ordering Information Part Number Temperature Range o o KS8993F 0 – KS8993FL 0 – hbwhelp@micrel.com KS8993F/FL Package C 128-PQFP C 128-PQFP M9999-052206 or (408) 955-1690 ...
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... Overview (section 2.1). Updated pin description for pin 22 to the following: VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD. VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the KS8993FL’s input power pins: VDDAP (pin 63), VDDC (pins 91, 123) and VDDA (pins 38, 43, 57) ...
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... Micrel, Inc. Table Of Contents 1 Signal Description .........................................................................................................................9 1.1 KS8993F Pin Diagram............................................................................................................................................................ 9 1.2 Pin Description and I/O Assignment..................................................................................................................................... 10 2 Functional Description ................................................................................................................20 2.1 Overview .............................................................................................................................................................................. 20 2.2 Media Converter Function .................................................................................................................................................... 20 2.2.1 OAM (Operations, Administration, and Management) Frame Format...................................................................... 20 2.2.2 MC (Media Converter) Mode ................................................................................................................................... 22 2.2.3 MC Loop Back Function........................................................................................................................................... 23 2 ...
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... Register 79 (0x4F): Shadow of 0x58h Register ................................................................................................................... 71 Register 80 (0x50): My Status 1 (Terminal and Center side)............................................................................................... 72 Register 81 (0x51): My Status 2 .......................................................................................................................................... 72 Register 82 (0x52): My Vendor Info (1) ............................................................................................................................... 73 Register 83 (0x53): My Vendor Info (2) ............................................................................................................................... 73 Register 84 (0x54): My Vendor Info (3) ............................................................................................................................... 73 Register 85 (0x55): My Model Info (1) ................................................................................................................................. 73 May 2006 5 hbwhelp@micrel.com KS8993F/FL M9999-052206 or (408) 955-1690 ...
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... Recommended Operating Conditions .................................................................................................................................. 86 5.3 Electrical Characteristics ...................................................................................................................................................... 87 5.4 100BASE-FX Electrical Specification ................................................................................................................................... 88 6 Timing Specifications ..................................................................................................................89 6.1 EEPROM Timing .................................................................................................................................................................. 89 6.2 SNI Timing ........................................................................................................................................................................... 90 6.3 MII Timing ............................................................................................................................................................................ 91 6.3.1 MAC Mode MII Timing ............................................................................................................................................. 91 6.3.2 PHY Mode MII Timing.............................................................................................................................................. 92 6.3.3 SPI Timing ............................................................................................................................................................... 92 May 2006 6 hbwhelp@micrel.com KS8993F/FL M9999-052206 or (408) 955-1690 ...
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... Micrel, Inc. 6.3.4 MDC/MDIO Timing .................................................................................................................................................. 95 6.3.5 Auto Negotiation Timing........................................................................................................................................... 96 6.4 Reset Timing ........................................................................................................................................................................ 97 6.5 Reset Circuit......................................................................................................................................................................... 98 7 Selection of Isolation Transformer ..............................................................................................99 8 Selection of Crystal/Oscillator .....................................................................................................99 9 Package Information .................................................................................................................100 May 2006 7 hbwhelp@micrel.com KS8993F/FL M9999-052206 or (408) 955-1690 ...
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... Figure 3: Auto Negotiation and Parallel Detection ............................................................................................................................. 29 Figure 4: Destination Address look up flowchart, stage 1 .................................................................................................................. 31 Figure 5: Destination Address resolution flowchart, stage 2 .............................................................................................................. 32 Figure 6: 802.1p Priority Field Format ............................................................................................................................................... 40 Figure 7: KS8993F EEPROM Configuration Timing Diagram............................................................................................................ 42 Figure 8: SPI Write Data Cycle.......................................................................................................................................................... 45 Figure 9: SPI Read Data Cycle.......................................................................................................................................................... 45 Figure 10: SPI Multiple Write ............................................................................................................................................................. 46 Figure 11: SPI Multiple Read ...
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... Micrel, Inc. 1 Signal Description 1.1 KS8993F Pin Diagram 103 PV32 104 PV21 105 PV23 106 DGND 107 VDDIO 108 PV12 109 PV13 110 P3_1PEN 111 P2_1PEN 112 P1_1PEN 113 P3_TXQ2 114 P2_TXQ2 115 P1_TXQ2 116 P3_PP 117 P2_PP 118 P1_PP 119 ...
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... ACT P2LED2 LINK P2LED1 FULL_DPX/COL P2LED0 SPEED Notes: LEDSEL0 is external strap-in pin #70. LEDSEL1 is external strap-in pin #23. P2LED3 is pin #20. During reset, P2LED[2:0] are inputs for internal testing. Digital ground 3.3V digital VDD 10 KS8993F/FL [0,1] ------ 100LINK/ACT 10LINK/ACT FULL_DPX [1,1] ------ ------ ------ ------ [0,1] ------ 100LINK/ACT 10LINK/ACT FULL_DPX ...
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... P2FFC Ipd 17 P1FST Opu 18 P1LCRCD Ipd May 2006 Description KS8993F operating modes, defined as below: (MCHS, MCCS) Description Normal 3 port switch mode (3 MAC + 2 PHY) MC mode is disabled. Port 1 is either Fiber or UTP. (0, 0) Port 2 is UTP. Port 3 (MII) is enabled. Center MC mode (3 MAC + 2 PHY) MC mode is enabled ...
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... Note: Internal pull down is weak; it will not turn ON the LED. See description in pin# (4). Digital ground VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD. VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the KS8993FL’s input power pins: VDDAP (pin 63), VDDC (pins 91, 123) and VDDA (pins 38, 43, 57) ...
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... Hardware reset pin (active low) Half Duplex Backpressure 1 = enable 0 = disable Special Mac Mode In this mode, the switch will do faster backoffs than normal enable 0 = disable LED display mode select See description in pin# (1,4). Switch MII transmit enable 13 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... Switch MII interface configuration (SCONF1, SCONF0) Description (0,0) disable, output tri-stated (0,1) PHY mode MII (1,0) MAC mode MII (1,1) PHY mode SNI Digital ground 1.8V digital VDD Priority Select Select queue servicing if using split queues. Use the table 14 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... I2C master/slave mode: serial data input/output See description in pin# (100, 101) SPI slave mode: chip select (active low) When SPIS_N is high, the KS8993F is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description in pin# (100, 101) ...
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... SPIS_N Ipu SPI chip select [PS1, PS0] = [1, 1] --- SMI mode In this mode, the KS8993F provides access to all its internal 8 bit registers thru its MDC and MDIO pins. Note When (PS1, PS0) ≠ (1,1), the KS8993F provides access to its 16 bit MIIM registers thru its MDC and MDIO pins. ...
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... Select transmit queue split on port split split The split sets up high and low priority queues. Packet priority classification is done on ingress ports, via port-based, 802.1p or TOS based scheme. The priority enabled queuing on port 1 is set by P1_TXQ2. Select port-based priority on port 3 ingress 17 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... Enable tag removal on port 2 egress 1 = enable 0 = disable All packets transmitted from port 2 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. Enable tag removal on port 1 egress 18 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... Ipu/O = input w/ internal pull up during reset, output pin otherwise; Ipd/O = input w/ internal pull down during reset, output pin otherwise strap pull down strap pull up; Otri = output tri-stated; Opu = Output with internal pull-up; Opd = Output with internal pull-down 19 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... The KS8993F implements the unique OAM sub-layer, which resides between RS and PCS layer in the IEEE 802.3 standard. The KS8993F sends and receives an OAM frame that has a fixed length of 96 bits. This special frame is used for the transmission of OAM information between center MC and terminal MC. ...
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... MC have to set always “0”) 0: Not Support Auto-Negotiation MC Auto- 1: Support Auto-Negotiation (Center side MC have to set always “0”) 0: one link partner on UTP side 1: multiple link partner on UTP side All bits must be set “0” Create FCS at this sub-layer (C0-M47) 21 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... OAM sub-layer generates and sends OAM frames, such as condition inform request, loop mode start request and loop mode stop request to the terminal MC. Media Cente Converte r OAM frame OAM frame Request command Reply command Media Terminal Converter May 2006 management Center office CPU Gateway / Router 22 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... MC Loop Back Function MC loop back operation is initiated and enabled by the center MC. The terminal MC provides the loop back path to return the loop back packet back to the center MC. In terminal MC mode, the KS8993F provides the following loop back path: • Receive loop back packet from center MC at RXP1/RXM1 input pins of port 1 (fiber). ...
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... May 2006 Type Description Input Hardware pin strapping to override the EEPROM value after reset When HWPOVR = 0, the reset sequence for KS8993F are: • Reads HW pin strapping configuration after reset. • Reads EEPROM configuration for all registers. When HWPOVR = 1, the reset sequence for KS8993F are: • ...
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... Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. 2.3.3 PLL Clock Synthesizer The KS8993F generates 125 MΗz, 31.25 MHz, 25 MΗz and 10 MΗz clocks for system timing. Internal clocks are generated from an external 25 MHz crystal or oscillator. 2.3.4 ...
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... Far-End Fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KS8993F detects a FEF when its FXSD1 input is between 1.0V and 1.8V. When a FEF occurs, the transmission side signals the link partner by sending 84 ones followed by 1 zero in the idle period between frames. ...
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... Power Management The KS8993F features a per-port power down mode. To save power, a port that is not being used can be powered down through the port control registers, or MIIM control registers. In addition, there is a full chip power down mode. When activated, the entire chip will be shut down. ...
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... A “Crossover Cable” connects a MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram depicts a typical “Crossover Cable” connection between two switches, or hubs (two MDI-X devices May 2006 Figure 1: Typical Straight Cable Connection Figure 2: Typical Crossover Cable Connection hbwhelp@micrel.com or (408) 955-1690 KS8993F/FL M9999-052206 ...
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... If auto negotiation is not supported or the link partner to the KS8993F is forced to bypass auto negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...
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... Forwarding The KS8993F will forward packets using an algorithm that is depicted in the following flowcharts. one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by Spanning Tree, Port Mirroring and Port VLAN processes to come up with “ ...
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... Search Static Table NOT FOUND FOUND Dynamic Table Search NOT FOUND Search complete. Get PTF1 from VLAN Table PTF1 31 KS8993F/FL -Search VLAN table -Ingress VLAN filtering -Discard NPVID check This search is based DA+FID This search is based on DA+FID M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... Micrel, Inc. Figure 5: Destination Address resolution flowchart, stage 2 Port Mirror Port VLAN Membership May 2006 PTF1 - RX Mirror - TX Mirror Process - Mirror - RX and TX Mirror Check PTF2 32 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... The KS8993F supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8993F receives a pause control frame, the KS8993F will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value from the second pause frame ...
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... The KS8993F will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8993F will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802 ...
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... MTXER would indicate a transmit error from the MAC device. appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8993F has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8993F has an MTXER pin, it should be tied low. ...
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... For the KS8993F, MIIM register access is selected when bit 2 of the PHY address is set to ‘0’. PHY address bits [4:3] are not defined for MIIM register access, and hence can be set to either 0’s or 1’s in read/write operation. May 2006 ...
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... For the KS8993F, SMI register access is selected when bit 2 of the PHY address is set to ‘1’. PHY address bits [1:0] are not defined for SMI register access, and hence can be set to either 0’s or 1’s in read/write operation. To access the KS8993F registers 0-127 (0x00 – 0x7F), the following applies: PHYAD[4:3] and REGAD[4:0] are concatenated to form the 7-bits address ...
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... A packet, received on port 1, is destined to port 2 after the internal look up. The KS8993F will forward the packet to both port 2 and port 3. The KS8993F can optionally forward even “bad” received packets to the “sniffer port”. ...
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... Dynamic MAC Table? No Yes Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KS8993F. These features can be set on a per port basis, and are defined in register 18, bit 6 and 5, respectively for port 1. 2.9.3 QoS Priority This feature provides Quality of Service (QoS) for applications, such as VoIP and video conferencing ...
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... Optionally, the Px_1PEN strap-in pins can be used to enable this feature. The KS8993F provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2 bytes Tag Control Information field (TCI), is also refer to as the 802 ...
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... Rate limiting is supported in both priority and non-priority environment. The rate limit starts from 0 kbps and goes up to the line rate in steps of 32 kbps. The KS8993F uses “one second” as the rate limiting interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. On the “ ...
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... RST_N SCL SDA The following is a sample procedure for programming the KS8993F with a pre-configured EEPROM: 1. Connect the KS8993F to the EEPROM by joining the SCL and SDA signals of the respective devices. For the KS8993F, SCL is pin 97 and SDA is pin 98 Enable I C master mode by setting the KS8993F strap-in pins, PS[1:0] (pins 100 and 101, respectively) to “00”. ...
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... Enable I C slave mode by setting the KS8993F strap-in pins PS[1:0] (pins 100 and 101 respectively) to “01”. 2. Power up the board and assert reset to the KS8993F. After reset, the “Start Switch” bit (register 1 bit 0) will be set to ‘0’. 3. Configure the desired register settings in the KS8993F, using the I 4. Read back and verify the register settings in the KS8993F, using the I 5. Write a ‘ ...
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... The KS8993F internal address counter will increment automatically to the next byte (next register) after the write. The next byte that is sent from the master device to the KS8993F SDA input pin will be written to the next register address. SPI multiple write will continue until the SPI master device terminates it by de- asserting the SPIS_N signal to the KS8993F ...
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... SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of SPIC. SPIS_N SPIC SPID SPIQ SPIS_N SPIC SPID SPIQ READ COMMAND May 2006 Figure 8: SPI Write Data Cycle WRITE COMMAND WRITE ADDRESS Figure 9: SPI Read Data Cycle READ ADDRESS 45 KS8993F/ WRITE DATA READ DATA M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... D6 D5 SPIQ SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID SPIQ May 2006 Figure 10: SPI Multiple Write WRITE COMMAND WRITE ADDRESS Byte 2 Byte 3 ... Figure 11: SPI Multiple Read READ ADDRESS Byte 2 Byte Byte Byte Byte Byte N hbwhelp@micrel.com KS8993F/ M9999-052206 or (408) 955-1690 ...
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... NOT SUPPORTED =1, force MDI (transmit on RXP/RXM pins) =0, normal operation (transmit on TXP/TXM pins) =1, disable auto MDI/MDI-X =0, normal operation =1, disable Far-End fault detection =0, normal operation =1, disable transmit =0, normal operation =1, disable LED =0, normal operation 47 KS8993F/FL Default Reference Reg. 28, bit 6 Reg. 44, bit Reg. 29, bit 3 Reg. 45, bit 3 ...
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... Far-End fault detected =0, No Far-End fault detected =1, Auto-Negotiation capable =0, Not Auto-Negotiation capable =1, Link is up =0, Link is down NOT SUPPORTED =0, Not extended register capable Description High order PHYID bits Description Low order PHYID bits 48 KS8993F/FL Default Reference 0 1 Always 1 1 Always 1 1 Always 1 1 Always 1 0 ...
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... Description NOT SUPPORTED NOT SUPPORTED NOT SUPPORTED Link partner pause capability Link partner 100 full capability Link partner 100 half capability Link partner 10 full capability Link partner 10 half capability 49 KS8993F/FL Defaul Reference Reg. 28, bit 4 Reg. 44, bit Reg ...
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... My Status 2 My Vendor Info (1) My Vendor Info (2) My Vendor Info (3) My Model Info (1) My Model Info (2) My Model Info (3) LNK Partner Status (1) LNK Partner Status (2) LNK Partner Vendor Info (1) LNK Partner Vendor Info (2) 50 Description Description Description hbwhelp@micrel.com KS8993F/FL M9999-052206 or (408) 955-1690 ...
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... PS0) = (0,1), (1,0), or (1,1) Description New back-off algorithm designed for UNH 1 = Enable 0 = Disable Used to classify priority for incoming 802.1Q packets. “user 51 Description hbwhelp@micrel.com KS8993F/FL Default 0x93 Default 0x0 - - Default 0x0 0x4 M9999-052206 ...
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... Length/Type field < 1500 enable age function in the chip = 0, disable age function in the chip = 1, turn on fast age (800 us enable more aggressive back off algorithm in half duplex mode to enhance performance. This is not an IEEE standard. 52 KS8993F/FL 0x0 0x1 0 0 return to normal (about Default 0 ...
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... Description = 1, 802.1Q VLAN mode is turned on. VLAN table needs to set up before the operation 802.1Q VLAN is disabled. 53 Protection” includes DA = hbwhelp@micrel.com KS8993F/FL Default SMAC (pin 69) value during reset 0 SMRXD0 (pin 85) ...
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... OR tx sniff (Either source port or destination port needs to match). This is the mode used to implement rx only sniff. Description =1, enable MII interface half duplex mode. =0, enable MII interface full duplex mode enable full duplex flow control on Switch MII interface disable full duplex flow control on Switch MII interface. 54 KS8993F/ Default 0 ...
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... The period is 67ms for 100BT or 500ms for 10BT. The default is 1%. Description Reserved Description Reserved Description Reserved 55 KS8993F/FL Pin SMRXD1 strap option. Pull down(0): Enable 100Mbps Pull up(1): Enable ...
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... LEDSEL1 is external strap-in pin #23. Reserved Description Reserved 56 Default 0 0 P1LCRCD (pin 18) value during reset 0 1 P1LPBM (pin 19) value during reset. This value needs to be “0”. LEDSEL0 (pin 70) value during reset [0, 1] ------ 100LINK/ACT 10LINK/ACT FULL_DPX [1, 1] ------ ------ ------ ------ 0 Default 0x00 M9999-052206 hbwhelp@micrel.com or (408) 955-1690 KS8993F/FL ...
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... KS8993F/FL Default 0x00 Default 0x00 ...
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... Define the port’s Port VLAN membership. Bit 2 stands for port 3, bit 1 for port 2, and bit 0 for port 1. The Port can only communicate within the membership. An ‘1’ includes a port in the membership; an ‘0’ excludes a port from the membership. 58 KS8993F/FL during reset: P1_TAGINS (port 1), P2_TAGINS (port 2), P3_TAGINS (port 3) ...
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... Description Port’s default tag, containing 7-5 : User Priority bits 4 : CFI bit 3-0 : VID[11:8] Description Port’s default tag, containing 7-0 : VID[7:0] 59 KS8993F/FL Default Pin value during reset: For port 1, P1FFC pin For port 2, P2FFC pin ...
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... Description This register along with port control 10, bits [7:4] form a 12- bits field to determine how many “32Kbps” low priority blocks can be received. (in a unit of 4K bytes in a one second period) 60 KS8993F/FL Default 0x00 Default 0x00 Default 0x0 0x0 ...
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... KS8993F/FL Default 0x0 0x0 Default ...
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... Full duplex capability = 0, suppress 10BT Full duplex capability from transmission to link partner = 1, advertise 10BT Half duplex capability = 0, suppress 10BT Half duplex capability from transmission to link partner 62 KS8993F/FL Default duplex are For port 1, P1ANEN pin value during reset For port 2, ...
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... Description = 1, MDI MDI = 1, AN done = 0, AN not done = 1, Link good = 0, Link not good = 1, link partner flow control (pause) capable = 0, link partner not flow control (pause) capable 63 KS8993F/FL Default Note: Only Port 1 supports fiber. This bit is applicable to port 1 only. ...
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... Receive flow control feature is active 0 = Receive flow control feature is inactive 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive 1 = link speed is 100Mbps 0 = link speed is 10Mbps 1 = link duplex is full 0 = link duplex is half 1 = Far-End fault status detected Far-End fault status detected 64 KS8993F/ Default ...
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... S6 to S10 to zero on Terminal MC side 0 = normal operation – supporting option disable “Indicate Center MC Condition” frame 0 = enable “Indicate Center MC condition” frame 1 = indicate change of status/value in registers # 0x50h, 0x51h, 0x58h, 0x59h, 0x5Dh, 0x5Eh, 0x5Fh. This bit is self-cleared after a read exclude the above situations 65 KS8993F/FL Defaul t 000 ...
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... Inform Request/Reply” frame, but the My Model Info bits MM24-MM47 will be mapped to Registers 4Ah-4Ch, instead of Registers 55h-57h. “Indicate Center/Terminal MC Condition” frame will be sent automatically. But this OAM frame can be sent manually using this command. 66 KS8993F/FL Default 001 ...
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... Center side UTP, the Terminal side will disable the TX on UTP and turn off the LEDs to its UTP. In Center side MC mode, this bit has no meaning. self-cleared after an ‘1’ is written to it. aintenance) sub-layer registers are not reset by this bit KS8993F/ ML_EN pin value during reset 0 ...
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... DA: Broadcast Data: 0F0F [Register #55h][Register #56h]([Register #57h] + 1). And the last byte ([Register #57h increments repeatedly by 1 the next loop back packet. [Register #55h][Register #56h][Register #57h] 68 Data: 55AA Data: 55AA Data: 0F0F Data: 0F0F hbwhelp@micrel.com or (408) 955-1690 KS8993F/FL Default Default 0 ...
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... Register 73 (0x49): Additional Status (Center and Terminal side) Bit Name R/W Description 7 Hard RO Hard Version (bits [7:6]) Version 1 6 Hard RO Version 0 5 Model RW Model Version (bits [5:4]): Version 1 4 Model RW others: Reserved Version 0 May 2006 : 00: 15km model 01: 40km model 69 KS8993F/FL Default Default Default Default ...
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... If Center MC sends the “Remote Command” in register 0x42h, this register value will be used for M39-M32 of the Maintenance frame, instead of register 6 AMM38 R/W 0x56h. 5 AMM37 R/W 4 AMM36 R/W [AMM39:AMM32] = bits[7:0] of the KS8993F address byte if the Operating 3 AMM35 R/W Mode in register 0x4Ah bits[1:0] is set to “10” 2 AMM34 R/W 1 AMM33 R/W May 2006 Terminal side ...
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... If Center MC sends the “Remote Command” in register 0x42h, this register value will be used for M47-M40 of the Maintenance frame, instead of register 6 AMM46 R/W 0x57h. 5 AMM45 R/W 4 AMM44 R/W [AMM47:AMM40] = bits[7:0] of the KS8993F data byte if the Operating Mode 3 AMM43 R/W in register 0x4Ah bits[1:0] is set to “10” 2 AMM42 R/W 1 AMM41 R/W 0 ...
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... For Terminal MC mode, this bit indicates the auto negotiation capability. For Center MC mode, this bit must always be “0” auto negotiation is supported 0 = auto negotiation is not supported May 2006 72 hbwhelp@micrel.com KS8993F/FL Default 0 1 (Terminal side) 0 (Center side DIAGF pin value DIAGF (Ipd) ...
Page 73
... MM47–MM40 RW May 2006 Description Description Description Description Note: If Remote Command feature is used, this register value can not be set to 0x22, 0x26, 0x2A and 0x2E. All other values are valid. Description Description 73 KS8993F/ Default 0x00 Default 0x00 Default 0x00 Default 0x00 Default 0x00 ...
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... Description This register has the same bits descriptions as register 80 (0x50). Description This register has the same bits descriptions as register 81 (0x51). Description Description Description Description Description Description 74 KS8993F/FL Default 0x47 (Center side) 0x07 (Terminal side) Default 0x00 Default 0x00 Default 0x00 Default ...
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... Register 103 (0x67): TOS Priority Control Register 7 Bit Name R/W 7-0 DSCP[7:0] R/W May 2006 Description Description Description Description Description Description Description Description 75 KS8993F/FL Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 M9999-052206 hbwhelp@micrel ...
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... MAC address table selected 01 = VLAN table selected 10 = dynamic MAC address table selected 11 = MIB counter selected Bit [9-8] of indirect address Description Bit [7-0] of indirect address 76 KS8993F/FL Default 0x00 Default 0x10 Default 0xA1 Default 0xFF Default 0xFF ...
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... Bit 39-32 of indirect data Description Bit 31-24 of indirect data Description Bit 23-16 of indirect data Description Bit 15-8 of indirect data Description Bit 7-0 of indirect data Description Reserved Qm_split status Description 77 KS8993F/FL Default 0_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default ...
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... Static MAC Address Table The KS8993F has both a static and a dynamic MAC address table. When a Destination Address (DA) look up is requested, both tables are searched to make a packet forwarding decision. When a Source Address (SA) look up is requested, only the dynamic table is searched for aging, migration and learning purposes. The static DA look up result will have precedence over the dynamic DA look up result ...
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... R/W 48 bits MAC Address nd entry) th entry) 79 KS8993F/FL Default 0000 000 0x0000_0000_000 0 M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... VID If 802.1Q VLAN mode is enabled, KS8993F will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place ...
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... MIB (Management Information Base) Counters The KS8993F provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet”. May 2006 ...
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... CRC (Upper limit depends on max packet size setting). Rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC (Upper limit depends on max packet size setting). The number of MAC control frames received by a port with 88-08h in EtherType field. 82 KS8993F/FL Default M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... Tx good broadcast packets (not including error broadcast or valid multicast packets) Tx good multicast packets (not including error multicast packets or valid broadcast packets) Tx good unicast packets Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium Tx total collision, half duplex only 83 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... Reserved RO Counter value Description TX packets dropped due to lack of resources TX packets dropped due to lack of resources TX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources 84 KS8993F/FL Default N/A 0 M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... A high performance SPI master is recommended to prevent counters overflow. 5. “Per Port” MIB Counters are designed as “read clear”. These counters will be cleared after they are read. 6. “All Port Dropped Packet” MIB counters are not cleared after they are read. May 2006 85 hbwhelp@micrel.com KS8993F/FL M9999-052206 or (408) 955-1690 ...
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... Supply Voltages Ambient Operating Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient May 2006 Symbol Min Typ VDDA, VDDAP, 1.710 1.8 VDDC VDDATX, VDDARX, 3.135 3.3 VDDIO θ hbwhelp@micrel.com KS8993F/FL Max Unit 1.890 V 3.465 V 70 °C 125 °C °C/W M9999-052206 or (408) 955-1690 ...
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... Micrel, Inc. 5.3 Electrical Characteristics Parameter Supply Current (including TX output driver current for KS8993F device only) 100BASE-TX operation (total) 100BASE- 10BASE-T operation (total) 10BASE 100BASE-TX (analog 100BASE-TX (digital 10BASE-T(analog 10BASE-T(digital TTL Inputs Input High Voltage Vih Input Low Voltage V il Input Current ...
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... May 2006 ) 100 Ω termination on the differential output. 100 Ω termination on the differential output. Test Condition 100 Ω termination on the differential output. 100 Ω termination on the differential output f 100BASE-FX mode 100BASE-FX mode 88 KS8993F/FL 2 Min Typ Max TBD TBD TBD TBD 0.95 1. ...
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... Output Valid May 2006 Figure 12: EEPROM Interface Input Timing Diagram ts1 tcyc1 Figure 13: EEPROM Interface Output Timing Diagram tcyc1 tov1 Table 17: EEPROM Timing Parameters Min 20 Hold time 20 4096 89 th1 Typ Max 16384 4112 4128 hbwhelp@micrel.com KS8993F/FL Unit M9999-052206 or (408) 955-1690 ...
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... Setup time th2 tov2 Output Valid May 2006 Figure 14: SNI Input Timing Diagram ts2 tcyc2 Figure 15: SNI Output Timing Diagram tcyc2 tov2 Table 18: SNI Timing Parameters Min 10 Hold time th2 Typ Max Unit 100 3 6 hbwhelp@micrel.com KS8993F/ M9999-052206 or (408) 955-1690 ...
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... Clock cycle (100BASE-TX) 100BASE-TX tcyc3 Clock cycle (10BASE-T) 10BASE-T ts3 Setup time th3 tov3 Output Valid May 2006 ts3 tcyc3 tcyc3 tov3 Table 19: MAC mode MII Timing Parameters Min 10 Hold time th3 Typ Max Unit 40 400 11 16 hbwhelp@micrel.com KS8993F/ M9999-052206 or (408) 955-1690 ...
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... Clock cycle (10BASE-T) 10BASE-T ts4 Setup time th4 tov4 Output Valid 6.3.3 SPI Timing May 2006 ts4 tcyc4 tcyc4 tov4 Table 20: PHY Mode MII Timing Parameters Min 10 Hold time th4 Typ Max 40 400 25 28 hbwhelp@micrel.com KS8993F/FL Unit M9999-052206 or (408) 955-1690 ...
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... Clock Fall Time tDLDH Data Input Rise Time tDHDL Data Input Fall Time May 2006 Figure 20: SPI Input Timing tSLCH tCHSH tCHDX tCLCH MSB tDLDH tDHDL High Impedance Table 21: SPI Input Timing Parameters Min 93 KS8993F/FL tSHSL tSHCH tCHCL LSB Max Units 5 MHz 100 ...
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... Clock High Time tCL Clock Low Time tQLQH SPIQ Rise Time tQHQL SPIQ Fall Time tSHQZ SPIQ Disable Time May 2006 Figure 21: SPI Output Timing tCH tCLQV Table 22: SPI Output Timing Parameters 94 KS8993F/FL tCL tSHQZ LSB tQLQH tQHQL Min Max Units 5 MHz ...
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... MDIO Setup to MDC (MDIO as input) MD1 t MDIO Hold after MDC (MDIO as input) MD2 t MDC to MDIO Valid (MDIO as output) MD3 May 2006 MD1 MD2 Valid Data t MD3 95 KS8993F/FL Valid Data Valid Data min. typ. max. 60ns 40% 60% 40% 60% 10ns 10ns 0ns 20ns M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... May 2006 Figure 23: Auto Negotiation Timing FLP FLP Burst Burst t FLPW t BTB Clock Data Pulse Pulse CTD t CTC 96 KS8993F/FL Clock Data Pulse Pulse min. typ. max. 8ms 16ms 24ms 2ms 100ns 55.5us 64us 69.5us 111us 128us 139us 17 33 M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...
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... Micrel, Inc. Reset Timing 6.4 The KS8993F should be powered up with the VDD core voltages applied before the VDDIO voltage. In the worst case, both VDD core and VDDIO voltages can be applied simultaneously. Additional, reset timing requirement are summarized in the following figure and table. ...
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... CPU, Figure 26 FPGA, etc),. At power-on-reset and D1 provide the necessary ramp rise time to reset the KS8993F device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up. Figure 26: Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output ...
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... Parameter Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.) The following are recommended transformers for the KS8993F. Magnetic Manufacturer Pulse Pulse (low cost) Transpower Bel Fuse Delta LanKom 8 Selection of Crystal/Oscillator A crystal or oscillator with the following typical characteristics is recommended ...
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... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. May 2006 Figure 27: 128-pin PQFP Package Outline Drawing © 2006 Micrel, Incorporated. 100 KS8993F/FL M9999-052206 hbwhelp@micrel.com or (408) 955-1690 ...