KS8993F-A1 Micrel Inc, KS8993F-A1 Datasheet
KS8993F-A1
Specifications of KS8993F-A1
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KS8993F-A1 Summary of contents
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... General Description The Micrel KS8993F is the industry’s first single chip Fast Ethernet Media Converter with built-in OAM functions. The KS8993F integrates three MACs, two PHYs, OAM, frame buffer and high performance switch into a single chip ideal for use in 100BASE-FX to 10BASE-T or 100BASE- TX conversion in the FTTx market ...
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... Voltages: Core 1.8V I/O and Transceiver 3.3V or 2.5V • Industrial Temperature • Available in 128-pin PQFP Ordering Information Part Number Temperature Range o KS8993F 0 – KS8993FL 0 – KS8993FI -40 – KS8993FLI -40 – Micrel Package o C 128-PQFP o C 128-PQFP o C 128-PQFP o C 128-PQFP Revision 1.0 ...
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... Overview (section 2.1). Updated pin description for pin 22 to the following: VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD. VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the KS8993FL’s input power pins: VDDAP (pin 63), VDDC (pins 91, 123) and VDDA (pins 38, 43, 57) ...
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... KS8993F Table Of Contents 1 Signal Description .........................................................................................................................9 1.1 KS8993F Pin Diagram............................................................................................................................................................ 9 1.2 Pin Description and I/O Assignment..................................................................................................................................... 10 2 Functional Description ................................................................................................................20 2.1 Overview .............................................................................................................................................................................. 20 2.2 Media Converter Function .................................................................................................................................................... 20 2.2.1 OAM (Operations, Administration, and Management) Frame Format...................................................................... 20 2.2.2 MC (Media Converter) Mode ................................................................................................................................... 22 2.2.3 MC Loop Back Function........................................................................................................................................... 22 2.2.4 Registers for Media Converter Functions ...
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... KS8993F 4 Register Map: Switch, MC, & PHY (8 bits registers) ..................................................................50 4.1 Global Registers................................................................................................................................................................... 51 Register 0 (0x00): Chip ID0 ................................................................................................................................................. 51 Register 1 (0x01): Chip ID1 / Start Switch ........................................................................................................................... 51 Register 2 (0x02): Global Control 0 ..................................................................................................................................... 51 Register 3 (0x03): Global Control 1 ..................................................................................................................................... 52 Register 4 (0x04): Global Control 2 ..................................................................................................................................... 53 Register 5 (0x05): Global Control 3 ..................................................................................................................................... 53 Register 6 (0x06): Global Control 4 ...
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... KS8993F Register 89 (0x59): LNK Partner Status (2)......................................................................................................................... 74 Register 90 (0x5A): LNK Partner Vendor Info (1) ............................................................................................................... 74 Register 91 (0x5B): LNK Partner Vendor Info (2) ................................................................................................................ 74 Register 92 (0x5C): LNK Partner Vendor Info (3)................................................................................................................ 74 Register 93 (0x5D): LNK Partner Model Info (1).................................................................................................................. 74 Register 94 (0x5E): LNK Partner Model Info (2).................................................................................................................. 74 Register 95 (0x5F): LNK Partner Model Info (3) ...
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... KS8993F 8 Selection of Crystal/Oscillator .....................................................................................................98 9 Package Information ...................................................................................................................99 August 26, 2004 - 7 - Micrel Revision 1.0 ...
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... Figure 3: Auto Negotiation and Parallel Detection ............................................................................................................................. 29 Figure 4: Destination Address look up flowchart, stage 1 .................................................................................................................. 31 Figure 5: Destination Address resolution flowchart, stage 2 .............................................................................................................. 32 Figure 6: 802.1p Priority Field Format ............................................................................................................................................... 40 Figure 7: KS8993F EEPROM Configuration Timing Diagram............................................................................................................ 42 Figure 8: SPI Write Data Cycle.......................................................................................................................................................... 45 Figure 9: SPI Read Data Cycle.......................................................................................................................................................... 45 Figure 10: SPI Multiple Write ............................................................................................................................................................. 46 Figure 11: SPI Multiple Read ...
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... KS8993F 1 Signal Description 1.1 KS8993F Pin Diagram 103 PV32 104 PV21 105 PV23 106 DGND 107 VDDIO 108 PV12 109 PV13 110 P3_1PEN 111 P2_1PEN 112 P1_1PEN 113 P3_TXQ2 114 P2_TXQ2 115 P1_TXQ2 116 P3_PP 117 P2_PP 118 P1_PP 119 P3_TAGINS ...
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... KS8993F 1.2 Pin Description and I/O Assignment Pin # Pin Name Type 1 P1LED2 I(pu)/O 2 P1LED1 I(pu)/O 3 P1LED0 I(pu)/O 4 P2LED2 I(pu)/O 5 P2LED1 I(pu)/O 6 P2LED0 I(pu)/O 7 DGND Gnd 8 VDDIO Pwr August 26, 2004 Description Port 1 LED indicators, defined as below: ...
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... P2FFC Ipd 17 P1FST Opu 18 P1LCRCD Ipd August 26, 2004 Description KS8993F operating modes, defined as below: (MCHS, MCCS) Description Normal 3 port switch mode (3 MAC + 2 PHY) MC mode is disabled. Port 1 is either Fiber or UTP. (0, 0) Port 2 is UTP. Port 3 (MII) is enabled. Center MC mode (3 MAC + 2 PHY) MC mode is enabled ...
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... Note: Internal pull down is weak; it will not turn ON the LED. See description in pin# (4). Digital ground VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD. VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the KS8993FL’s input power pins: VDDAP (pin 63), VDDC (pins 91, 123) and VDDA (pins 38, 43, 57) ...
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... KS8993F Pin # Pin Name Type 34 ML_EN Ipd 35 DIAGF Ipd 36 PWRDN I 37 AGND Gnd 38 VDDA Pwr 39 AGND Gnd 40 MUX1 I 41 MUX2 I 42 AGND Gnd 43 VDDA Pwr 44 FXSD1 I 45 RXP1 I/O 46 RXM1 I/O 47 AGND Gnd 48 TXP1 I/O 49 TXM1 I/O 50 VDDATX Pwr 51 VDDARX Pwr ...
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... KS8993F Pin # Pin Name Type 72 SMTXD3 Ipd 73 SMTXD2 Ipd 74 SMTXD1 Ipd 75 SMTXD0 Ipd 76 SMTXER Ipd 77 SMTXC Ipd/O 78 DGND Gnd 79 VDDIO Pwr 80 SMRXC Ipd/O 81 SMRXDV O 82 SMRXD3 Ipd/O 83 SMRXD2 Ipd / O 84 SMRXD1 Ipd/O 85 SMRXD0 Ipd/O 86 SCOL Ipd/O 87 SCRS Ipd/O 88 SCONF1 Ipd 89 SCONF0 ...
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... I2C master/slave mode: serial data input/output See description in pin# (100, 101) SPI slave mode: chip select (active low) When SPIS_N is high, the KS8993F is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description in pin# (100, 101) ...
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... SPIS_N Ipu SPI chip select [PS1, PS0] = [1, 1] --- SMI mode In this mode, the KS8993F provides access to all its internal 8 bit registers thru its MDC and MDIO pins. Note When (PS1, PS0) ≠ (1,1), the KS8993F provides access to its 16 bit MIIM registers thru its MDC and MDIO pins. ...
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... KS8993F Pin # Pin Name Type 108 PV12 Ipu 109 PV13 Ipu 110 P3_1PEN Ipd 111 P2_1PEN Ipd 112 P1_1PEN Ipd 113 P3_TXQ2 Ipd 114 P2_TXQ2 Ipd 115 P1_TXQ2 Ipd 116 P3_PP Ipd August 26, 2004 Description Port 1 port based VLAN mask bits. Use to select which ports may transmit packets received on port 1 ...
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... KS8993F Pin # Pin Name Type 117 P2_PP Ipd 118 P1_PP Ipd 119 P3_TAGINS Ipd 120 P2_TAGINS Ipd 121 P1_TAGINS Ipd 122 DGND Gnd 123 VDDC Pwr 124 P3_TAGRM Ipd 125 P2_TAGRM Ipd 126 P1_TAGRM Ipd August 26, 2004 Description Select port-based priority on port 2 ingress ...
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... KS8993F Pin # Pin Name Type 127 TESTEN Ipd 128 SCANEN Ipd Note: Pwr = power supply; Gnd = ground input output; I/O = bi-directional Ipu = input w/ internal pull up; Ipd = input w/ internal pull down; August 26, 2004 Description Scan Test Enable For normal operation, pull down this pin to ground ...
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... The KS8993F implements the unique OAM sub-layer, which resides between RS and PCS layer in the IEEE 802.3 standard. The KS8993F sends and receives an OAM frame that has a fixed length of 96 bits. This special frame is used for the transmission of OAM information between center MC and terminal MC. ...
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... KS8993F Bit Command F0-F7 Preamble C0 Conservation Delimiter C1 Direction Delimiter C2-C3 Configuration Delimiter C4-C7 Version C8-C15 Control signal S0 Power S1 Optical S2 UTP link Way for information S5 Loop mode Terminal S6 option Terminal S7 Speed1 Terminal S8 Speed2 Terminal S9 Duplex Terminal S10 Negotiation capability S11 Multiple link partner S12 – ...
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... KS8993F 2.2.2 MC (Media Converter) Mode MC (Media Converter) mode is selected and configured using hardware pins: MCCS and MCHS. Terminal MC mode without port 3 support is enabled when MCCS=0 and MCHS=1. In this mode, port 1 is 100BASE- FX, port 2 is 10BASE-TX or 100BASE-TX and port 3 is disabled. Terminal MC function is enabled, and the OAM sub- layer responds to the center MC with OAM frames, such as condition inform reply, loop mode start reply, and loop mode stop reply ...
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... KS8993F MC loop back operation is initiated and enabled by the center MC. The terminal MC provides the loop back path to return the loop back packet back to the center MC. In terminal MC mode, the KS8993F provides the following loop back path: • Receive loop back packet from center MC at RXP1/RXM1 input pins of port 1 (fiber). ...
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... When HWPOVR = 0, the reset sequence for KS8993F are: • Reads HW pin strapping configuration after reset. • Reads EEPROM configuration for all registers. When HWPOVR = 1, the reset sequence for KS8993F are: • Reads HW pin strapping configuration after reset. • Reads EEPROM configuration for all registers, except for port 2 (auto negotiation, speed, duplex) and Missing Link ...
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... Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. 2.3.3 PLL Clock Synthesizer The KS8993F generates 125 MΗz, 31.25 MHz, 25 MΗz and 10 MΗz clocks for system timing. Internal clocks are generated from an external 25 MHz crystal or oscillator. 2.3.4 Scrambler/De-scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander ...
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... Power Management The KS8993F features a per-port power down mode. To save power, a port that is not being used can be powered down through the port control registers, or MIIM control registers. In addition, there is a full chip power down mode. When activated, the entire chip will be shut down. ...
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... CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the KS8993F device. This feature can be extremely useful when the end users are unaware of cable type differences, and can also save on an additional uplink configuration connection. ...
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... KS8993F “Crossover Cable” connects a MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram depicts a typical “Crossover Cable” connection between two switches, or hubs (two MDI-X devices August 26, 2004 Figure 1: Typical Straight Cable Connection Figure 2: Typical Crossover Cable Connection ...
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... If auto negotiation is not supported or the link partner to the KS8993F is forced to bypass auto negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...
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... Forwarding The KS8993F will forward packets using an algorithm that is depicted in the following flowcharts. one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by Spanning Tree, Port Mirroring and Port VLAN processes to come up with “ ...
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... KS8993F Figure 4: Destination Address look up flowchart, stage 1 PTF1 = NULL Search complete. Get PTF1 from Static MAC Table Search complete. Get PTF1 from Dynamic MAC Table August 26, 2004 Start NO VLAN ID valid? YES FOUND Search Static Table NOT FOUND FOUND Dynamic Table Search ...
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... KS8993F Figure 5: Destination Address resolution flowchart, stage 2 August 26, 2004 PTF1 - RX Mirror Port Mirror - TX Mirror Process - Mirror - RX and TX Mirror Port VLAN Membership Check PTF2 - 32 - Micrel Revision 1.0 ...
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... If a transmit packet experiences collisions after 512 bit times of the transmission, the packet will be dropped. 2.4.10 Illegal Frames The KS8993F discards frames less than 64 bytes long and can be programmed to accept frames up to 1536 bytes long in Global Register 4 (0x04). For special applications, the KS8993F can also be programmed to accept frames up to 1916 bytes long in the same global register ...
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... The KS8993F will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8993F will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802 ...
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... MTXER would indicate a transmit error from the MAC device. appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8993F has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8993F has an MTXER pin, it should be tied low. ...
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... Write 32 1’s 01 For the KS8993F, MIIM register access is selected when bit 2 of the PHY address is set to ‘0’. PHY address bits [4:3] are not defined for MIIM register access, and hence can be set to either 0’s or 1’s in read/write operation. 2.8 ...
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... For the KS8993F, SMI register access is selected when bit 2 of the PHY address is set to ‘1’. PHY address bits [1:0] are not defined for SMI register access, and hence can be set to either 0’s or 1’s in read/write operation. To access the KS8993F registers 0-127 (0x00 – 0x7F), the following applies: PHYAD[4:3] and REGAD[4:0] are concatenated to form the 7-bits address ...
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... A packet, received on port 1, is destined to port 2 after the internal look up. The KS8993F will forward the packet to both port 2 and port 3. The KS8993F can optionally forward even “bad” received packets to the “sniffer port”. ...
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... No Yes Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KS8993F. These features can be set on a per port basis, and are defined in register 18, bit 6 and 5, respectively for port 1. 2.9.3 QoS Priority This feature provides Quality of Service (QoS) for applications, such as VoIP and video conferencing. The KS8993F per port transmit queue could be split into two priority queues: a high priority queue and a low priority queue ...
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... Optionally, the Px_1PEN strap-in pins can be used to enable this feature. The KS8993F provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2 bytes Tag Control Information field (TCI), is also refer to as the 802 ...
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... Rate limiting is supported in both priority and non-priority environment. The rate limit starts from 0 kbps and goes up to the line rate in steps of 32 kbps. The KS8993F uses “one second” as the rate limiting interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. On the “ ...
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... RST_N SCL SDA The following is a sample procedure for programming the KS8993F with a pre-configured EEPROM: 1. Connect the KS8993F to the EEPROM by joining the SCL and SDA signals of the respective devices. For the KS8993F, SCL is pin 97 and SDA is pin 98 Enable I C master mode by setting the KS8993F strap-in pins, PS[1:0] (pins 100 and 101, respectively) to “ ...
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... Enable I C slave mode by setting the KS8993F strap-in pins PS[1:0] (pins 100 and 101 respectively) to “01”. 2. Power up the board and assert reset to the KS8993F. After reset, the “Start Switch” bit (register 1 bit 0) will be set to ‘0’. 3. Configure the desired register settings in the KS8993F, using the I 4. Read back and verify the register settings in the KS8993F, using the I 5. Write a ‘ ...
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... Enable SPI slave mode by setting the KS8993F strap-in pins PS[1:0] (pins 100 and 101 respectively) to “10”. 3. Power up the board and assert reset to the KS8993F. After reset, the “Start Switch” bit (register 1 bit 0) will be set to ‘0’. 4. Configure the desired register settings in the KS8993F, using the SPI write or multiple write command. ...
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... KS8993F The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of SPIC. ...
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... KS8993F SPIS_N SPIC SPID X 0 SPIQ SPIS_N SPIC SPID SPIQ SPIS_N SPIC SPID X 0 SPIQ SPIS_N SPIC SPID SPIQ August 26, 2004 Figure 10: SPI Multiple Write WRITE COMMAND WRITE ADDRESS Byte 2 Byte 3 ... Figure 11: SPI Multiple Read READ COMMAND READ ADDRESS Byte 2 Byte 3 ...
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... KS8993F 3 MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C and SMI interfaces can also be used to access these registers. The latter three interfaces use a different mapping mechanism than the MIIM interface. ...
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... KS8993F 15 T4 capable RO 14 100 Full RO capable 13 100 Half RO capable 12 10 Full RO capable 11 10 Half RO capable 10-7 Reserved RO 6 Preamble RO suppressed 5 AN complete RO 4 Far-End fault capable RO 2 Link status RO 1 Jabber test RO 0 Extended RO capable Register 2: PHYID HIGH Bit Name ...
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... KS8993F Register 4: Auto-Negotiation Advertisement Ability Bit Name R/W 15 Next page RO 14 Reserved RO 13 Remote fault RO 12-11 Reserved RO 10 Pause R/W 9 Reserved R/W 8 Adv 100 Full R/W 7 Adv 100 Half R/W 6 Adv 10 Full R/W 5 Adv 10 Half R/W 4-0 Selector field RO Register 5: Auto-Negotiation Link Partner Ability ...
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... KS8993F 4 Register Map: Switch, MC, & PHY (8 bits registers) Global Registers Register Register (Decimal) (Hex) 0-1 0x00 - 0x01 2-11 0x02 - 0x0B 12 0x0C 13-15 0x0D - 0x0F Port Registers Register Register (Decimal) (Hex) 16-29 0x10 – 0x1D 30-31 0x1E – 0x1F 32-45 0x20 – 0x2D 46-47 0x2E – ...
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... KS8993F 93 0x5D 94 0x5E 95 0x5F Advanced Control Registers Register Register (Decimal) (Hex) 96-103 0x60-0x67 104-109 0x68-0x6D 110-111 0x6E-0x6F 112-120 0x70-0x78 121-122 0x79-0x7A 123-124 0x7B-0x7C 125-126 0x7D-0x7E 127 0x7F 4.1 Global Registers Register 0 (0x00): Chip ID0 Bit Name R/W 7-0 Family ID RO Register 1 (0x01): Chip ID1 / Start Switch ...
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... KS8993F 3 Pass flow R/W control packet 2 Buffer share R/W mode 1 Reserved R/W 0 Link change R/W age Register 3 (0x03): Global Control 1 Bit Name R/W 7 Pass all R/W frames 6 Repeater R/W Mode 5 IEEE 802.3x R/W Transmit direction flow control enable 4 IEEE 802.3x R/W ...
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... KS8993F Register 4 (0x04): Global Control 2 Bit Name R/W 7 Unicast R/W port-VLAN mismatch discard 6 Multicast R/W Storm protection Disable 5 Back R/W pressure mode 4 Flow control R/W and back pressure fair mode 3 No excessive R/W collision drop 2 Huge packet R/W support 1 Legal R/W ...
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... KS8993F 5 Reserved R/W 4 Reserved R/W 3-2 Priority R/W Scheme select 1 Reserved R/W 0 Sniff mode R./W select Register 6 (0x06): Global Control 4 Bit Name R/W 7 Reserved R/W 6 Switch MII R/W half duplex mode 5 Switch MII R/W flow control enable 4 Switch MII R/W 10BT ...
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... KS8993F 3 Null VID R/W replacemen t 2-0 Broadcast R/W storm protection rate Bit [10:8] Register 7 (0x07): Global Control 5 Bit Name R/W 7-0 Broadcast R/W storm protection rate Bit [7:0] 100BT Rate: 148,800 frames/sec * 67 ms/interval * frames/interval (approx.) = 0x63 Register 8 (0x08): Global Control 6 Bit ...
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... KS8993F 6 PHY power R/W save 5 CRC drop R/W 4 Reserved RW 3 MCLBM1 R/W 2 MCLBM0 R/W 1 LED mode R/W 0 Reserved R/W Register 12 (0x0C): Reserved Register Bit Name R/W 7-0 Reserved Register 13 (0x0D): User Defined Register 1 Bit Name R/W 7-0 UDR1 R/W August 26, 2004 ...
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... KS8993F Register 14 (0x0E): User Defined Register 2 Bit Name R/W 7-0 UDR2 R/W Register 15 (0x0F): User Defined Register 3 Bit Name R/W 7-0 UDR3 R/W 4.2 Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated ...
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... KS8993F 1 Tag removal R/W 0 Priority R/W Enable Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Bit Name R/W 7 Sniffer port R/W 6 Receive sniff R/W 5 Transmit sniff R/W 4 Double tag R/W 3 Reserved R/W 2-0 Port VLAN R/W membership ...
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... KS8993F 5 Discard Non R/W PVID packets 4 Force flow R/W control 3 Back R/W pressure enable 2 Transmit R/W enable 1 Receive R/W enable 0 Learning R/W disable Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Bit Name R/W 7-0 Default tag ...
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... KS8993F Bit Name R/W 7-0 Transmit high R/W priority rate control [7:0] Register 22 (0x16): Port 1 Control 6 Register 38 (0x26): Port 2 Control 6 Register 54 (0x36): Port 3 Control 6 Bit Name R/W 7-0 Transmit low R/W priority rate control [7:0] Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 ...
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... KS8993F Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 Bit Name R/W 7 Receive R/W differential priority rate control 6 Low priority R/W receive rate control enable 5 High priority R/W receive rate control enable 4 Low priority R/W receive rate ...
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... KS8993F 6 Force R/W Speed 5 Force R/W duplex 4 Advertised R/W flow control capability 3 Advertised R/W 100BT Full duplex capability 2 Advertised R/W 100BT Half duplex capability 1 Advertised R/W 10BT Full duplex capability 0 Advertised R/W 10BT Half duplex capability Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 ...
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... KS8993F 3 Power down R/W 2 Disable auto R/W MDI/MDI-X 1 Force MDI R/W 0 Reserve R/W Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Reserved, not applied to port 3 Bit Name R/W 7 MDI-X status done RO 5 Link good RO 4 Partner flow RO control capability ...
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... KS8993F Register 31 (0x1F): Port 1 Status 1 Register 47 (0x2F): Port 2 Status 1 Register 63 (0x3F): Port 3 Status 1 Bit Name R/W 7 Reserved RO 6-5 Reserved RO 4 Receive flow RO control enable 3 Transmit flow RO control enable 2 Operation RO Speed 1 Operation Ro duplex 0 Far-End fault RO August 26, 2004 Description 1 = Receive flow control feature is active ...
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... KS8993F 4.3 Media Converter Registers Register 64 (0x40): PHY Address Bit Name R/W 7–5 Reserved RO 4 Addr4 R/W 3 Addr3 R/W 2 Addr2 R/W 1 Addr1 R/W 0 Addr0 R/W Register 65 (0x41): Center Side Status Bit Name R/W 7 BUSY RO 6 Vendor mode R/W 5–3 Reserved RO 2 Option b ...
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... KS8993F Note: This register is managed by the Center side. Register 66 (0x42): Center Side Command Bit Name R/W Description 7–5 Timer R/W 000 = Reserved (Do Not Use) Delay 001 = 32us (default) 010 = 128us 011 = 256us 100 = 512us 101 = 1ms 110 = 2m 111 = 4ms 4 Com4 R/W To send a maintenance frame, an external controller writes to these command bits via the SMI, SPI, or I2C interface ...
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... KS8993F 4 SW reset R reset MC sub-layer, MACs of both PHY ports and switch fabric normal operation 3 Remote R enable “Remote Command” access at Center side and Terminal Command Enable 0 = disable “Remote Command” access at Center side and Terminal 2 Enhanced R defined as follows: ML_EN its 0 = normal operation ...
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... KS8993F Register 68 (0x44): Loop Back Setup1 Bit Name R/W Description 7 T7 R/W Center and Terminal sides 6 T6 R/W 0000_0000 : Clear valid transmit and valid receive counters in registers 4Dh R/W Center side only 1 T1 R/W 0000_0001 : Send 1 MC loop back packet ...
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... KS8993F Register 70 (0x46): Loop Back Result Counter for CRC Error Bit Name R/W Description 7 CRC7 RO Center side only 6 CRC6 RO This counter is incremented when loop back packet has CRC error. 5 CRC5 RO 4 CRC4 RO 0000_0000 : No CRC error received 3 CRC4 RO 0000_0001 : 1 CRC error received ...
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... If Center MC sends the “Remote Command” in register 0x42h, this register value will be used for M39-M32 of the Maintenance frame, instead of register 6 AMM38 R/W 0x56h. 5 AMM37 R/W 4 AMM36 R/W [AMM39:AMM32] = bits[7:0] of the KS8993F address byte if the Operating 3 AMM35 R/W Mode in register 0x4Ah bits[1:0] is set to “10” 2 AMM34 R/W 1 AMM33 R/W 0 ...
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... If Center MC sends the “Remote Command” in register 0x42h, this register value will be used for M47-M40 of the Maintenance frame, instead of register 6 AMM46 R/W 0x57h. 5 AMM45 R/W 4 AMM44 R/W [AMM47:AMM40] = bits[7:0] of the KS8993F data byte if the Operating Mode 3 AMM43 R/W in register 0x4Ah bits[1:0] is set to “10” 2 AMM42 R/W 1 AMM41 R/W 0 ...
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... KS8993F Register 80 (0x50): My Status 1 (Terminal and Center side) Bit Name R/W Description H-MC Link speed H-MC Link Option 1 = Terminal MC mode 0 = Center MC mode Loop back mode indication loop back state (CST1, CST2, UST1 Normal 4 S4 R/W Loss of optical signal notification 1 = use FEFI ...
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... KS8993F For Center MC mode, this bit is always “0” Full Duplex 0 = Half Duplex, or Register 0x50h bit[2] is “1” (UTP link is down For Terminal MC mode, this bit indicates the UTP port’s SPEED status. For Center MC mode, this bit is always “0”. ...
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... KS8993F Register 88 (0x58): LNK Partner Status (1) Bit Name R/W 7-0 LS7–LS0 RO Register 89 (0x59): LNK Partner Status (2) Bit Name R/W 7-0 LS15–LS8 RO Register 90 (0x5A): LNK Partner Vendor Info (1) Bit Name R/W 7-0 LM7–LM0 RO Register 91 (0x5B): LNK Partner Vendor Info (2) ...
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... KS8993F 4.4 Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit DSCP (Differentiated Services Code Point) register used to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register bit the priority is high ...
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... KS8993F Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address for MAC pause control frames. Register 104 (0x68): MAC Address Register 0 Bit Name R/W 7-0 MACA[47:40] R/W Register 105 (0x69): MAC Address Register 1 ...
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... KS8993F Register 112 (0x70): Indirect Data Register 8 Bit Name R/W 68-64 Indirect data R/W Register 113 (0x71): Indirect Data Register 7 Bit Name R/W 63-56 Indirect data R/W Register 114 (0x72): Indirect Data Register 6 Bit Name R/W 55-48 Indirect data R/W Register 115 (0x73): Indirect Data Register 5 ...
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... Static MAC Address Table The KS8993F has both a static and a dynamic MAC address table. When a Destination Address (DA) look up is requested, both tables are searched to make a packet forwarding decision. When a Source Address (SA) look up is requested, only the dynamic table is searched for aging, migration and learning purposes. The static DA look up result will have precedence over the dynamic DA look up result ...
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... KS8993F Bit Name 57-54 FID 53 Use FID 52 Override 51 Valid 50-48 Forwarding ports 47-0 MAC address Examples: 1) Static Address Table Read (read the 2 Write to reg. 110 with 0x10 (read static table selected) Write to reg. 111 with 0x01 (trigger the read operation) Then Read reg ...
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... VID If 802.1Q VLAN mode is enabled, KS8993F will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place ...
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... MIB (Management Information Base) Counters The KS8993F provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet”. August 26, 2004 ...
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... KS8993F Bit Name 31 Reserve 30 Count Valid 29-0 Counter Values “Per Port” MIB Counters are read using indirect memory access. The base address offsets and address ranges for all three ports are: Port 1 : base is 0x00 and range is (0x00-0x1f) Port 2 : base is 0x20 and range is (0x20-0x3f) Port 3 : base is 0x40 and range is (0x40-0x5f) Port 1’ ...
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... KS8993F 0xB RxBroadcast 0xC RxMulticast 0xD RxUnicast 0xE Rx64Octets 0xF Rx65to127Octets 0x10 Rx128to255Octets 0x11 Rx256to511Octets 0x12 Rx512to1023Octets 0x13 Rx1024to1522Octets 0x14 TxLoPriorityByte 0x15 TxHiPriorityByte 0x16 TxLateCollision 0x17 TxPausePkts 0x18 TxBroadcastPkts 0x19 TxMulticastPkts 0x1A TxUnicastPkts 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision 0x1E TxSingleCollision ...
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... KS8993F 0x1F TxMultipleCollision Table 15: Format of “All Port Dropped Packet” MIB Counters Bit Name 30-16 Reserved 15-0 Counter values “All Port Dropped Packet” MIB Counters are read using indirect memory access. The address offsets for these counters are shown in the following table: Table 16: “ ...
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... KS8993F Read reg. 120 (counter value 7-0) NOTES: 1. Both “Per Port” and “All Port Dropped Packet” MIB Counters do not indicate overflow. The application must keep track of overflow conditions for these counters. 2. “All Port Dropped Packet” MIB Counters do not indicate if count is valid. The application must keep track of valid conditions for these counters ...
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... KS8993F 5 Electrical Specifications Stresses greater than those listed in this table may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level ...
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... KS8993F 5.3 Electrical Characteristics Parameter Supply Current (including TX output driver current for KS8993F device only) 100BASE-TX operation (total) 100BASE- 10BASE-T operation (total) 10BASE 100BASE-TX (analog 100BASE-TX (digital 10BASE-T(analog 10BASE-T(digital TTL Inputs Input High Voltage Vih Input Low Voltage V il Input Current ...
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... KS8993F Peak Differential Output V p Voltage Jitters Added Rise/Fall time 5.4 100BASE-FX Electrical Specification Parameter Sym Supply Current (including FX output driver current) 100BASE-FX operation - total 100BASE-FX (transmitter 100BASE-FX (analog 100BASE-FX (digital 100BASE-FX Transmit Peak Differential Output V o Voltage Output Voltage Imbalance ...
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... KS8993F 6 Timing Specifications 6.1 EEPROM Timing Receive Timing SCL SDA Transmit Timing SCL SDA Timing Description Parameter tcyc1 Clock cycle ts1 Setup time th1 tov1 Output Valid August 26, 2004 Figure 12: EEPROM Interface Input Timing Diagram ts1 tcyc1 Figure 13: EEPROM Interface Output Timing Diagram ...
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... KS8993F 6.2 SNI Timing Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Timing Description Parameter tcyc2 Clock cycle ts2 Setup time th2 tov2 Output Valid August 26, 2004 Figure 14: SNI Input Timing Diagram ts2 tcyc2 Figure 15: SNI Output Timing Diagram ...
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... KS8993F 6.3 MII Timing 6.3.1 MAC Mode MII Timing Figure 16: MAC Mode MII Timing - Data received from MII Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 17: MAC Mode MII Timing - Data transmitted to MII Transmit Timing MTXCLK MRXDV MRXD[3:0] Timing Description Parameter tcyc3 ...
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... KS8993F 6.3.2 PHY Mode MII Timing Figure 18: PHY Mode MII Timing – Data received from MII Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 19: PHY Mode MII Timing - Data transmitted to MII Transmit Timing MRXCLK MRXDV MRXD[3:0] Timing Description Parameter tcyc4 Clock cycle ...
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... KS8993F SPIS_N tCHSL SPIC tDVCH SPID SPIQ Timing Description Parameter fC Clock Frequency tCHSL SPIS_N Inactive Hold Time tSLCH SPIS_N Active Setup Time tCHSH SPIS_N Active Hold Time tSHCH SPIS_N Inactive Setup Time tSHSL SPIS_N Deselect Time tDVCH Data Input Setup Time ...
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... KS8993F SPIS_N SPIC SPIQ SPID Timing Description Parameter fC Clock Frequency tCLQX SPIQ Hold Time tCLQV Clock Low to SPIQ Valid tCH Clock High Time tCL Clock Low Time tQLQH SPIQ Rise Time tQHQL SPIQ Fall Time tSHQZ SPIQ Disable Time August 26, 2004 ...
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... KS8993F 6.3.4 MDC/MDIO Timing Figure 22: MDC/MDIO Timing for MIIM and SMI Interfaces MDC MDIO (Into Chip) MDIO (Out of Chip) t MDC period P t MDC pulse width WL t MDC pulse width WH t MDIO Setup to MDC (MDIO as input) MD1 t MDIO Hold after MDC (MDIO as input) ...
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... KS8993F 6.3.5 Auto Negotiation Timing TX+/TX- TX+/TX- t FLP burst to FLP burst BTB t FLP burst width FLPW t Clock/Data pulse width PW t Clock pulse to data pulse CTD t Clock pulse to clock pulse CTC Number of Clock/Data pulses per burst August 26, 2004 Figure 23: Auto Negotiation Timing ...
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... KS8993F Reset Timing 6.4 As long as the stable supply voltages to reset high timing (minimum of 10 ms) is met, there is no power sequencing requirement for the KS8993F supply voltages (1.8V, 3.3/2.5V). The reset timing requirement is summarized in the following figure and table. Supply Voltage RST_N ...
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... Parameter Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.) The following are recommended transformers for the KS8993F. Magnetic Manufacturer Pulse Pulse (low cost) Transpower Bel Fuse Delta LanKom 8 Selection of Crystal/Oscillator A crystal or oscillator with the following typical characteristics is recommended ...
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... KS8993F 9 Package Information Micrel is a registered trademark of Micrel and its subsidiaries in the United States and certain other countries. All other trademarks are the The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury ...