KS8993F-A1 Micrel Inc, KS8993F-A1 Datasheet - Page 43

• Manufacturer Part Number: KS8993F-A1
• Description: IC CONV MED 10/100 3PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8993F-A1

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• For Use With: KS8993F-EVAL - EVAL KIT EXPERIMENTAL KS8993F
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

KS8993F
2.10.2 I
In managed mode, the KS8993F can be configured as an I
(external controller/CPU) has complete programming access to the KS8993F’s 128 registers. Programming access
includes the Global Registers, Port Registers, Media Converter Registers, Advanced Control Registers and indirect
access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters
are indirectly accessed via registers 110 thru 120.
In I
similar to addressing Atmel’s AT24C02 EEPROM’s memory locations. Details of I
timing information can be found in the AT24C02 Datasheet.
Two fixed 8 bit device addresses are used to address the KS8993F in I
write. The addresses are as follow:
The following is a sample procedure for programming the KS8993F using the I
2.10.3 SPI Slave Serial Bus Configuration
In managed mode, the KS8993F can be configured as a SPI slave device. In this mode, a SPI master device (external
controller/CPU) has complete programming access to the KS8993F’s 128 registers. Programming access includes
the Global Registers, Port Registers, Media Converter Registers, Advanced Control Registers and indirect access to
the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are
indirectly accessed via registers 110 thru 120.
The KS8993F supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write. SPI
multiple read and multiple write are also supported by the KS8993F to expedite register read back and register
configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KS8993F SPIS_N input pin (SPI Slave
Select signal) low after a byte (a register) is read. The KS8993F internal address counter will increment automatically
to the next byte (next register) after the read. The next byte at the next register address will be shifted out onto the
KS8993F SPIQ output pin. SPI multiple read will continue until the SPI master device terminates it by de-asserting the
SPIS_N signal to the KS8993F.
August 26, 2004
2
C slave mode, the KS8993F operates like other I
1. Enable I
2. Power up the board and assert reset to the KS8993F. After reset, the “Start Switch” bit (register 1 bit 0) will be
3. Configure the desired register settings in the KS8993F, using the I
4. Read back and verify the register settings in the KS8993F, using the I
5. Write a ‘1’ to the “Start Switch” bit to start the KS8993F with the programmed settings.
1011_1111
1011_1110
set to ‘0’.
Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and
“Power down” can be programmed after the switch has been started.
2
C Slave Serial Bus Configuration
2
C slave mode by setting the KS8993F strap-in pins PS[1:0] (pins 100 and 101 respectively) to “01”.
<read>
<write>
2
C slave devices. Addressing the KS8993F’s 8 bit registers is
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2
C slave device. In this mode, an I
2
C slave mode. One is for read; the other is for
2
C write operation.
2
C read operation.
2
C slave serial bus:
2
C read/write operations and related
2
C master device
Revision 1.0
Micrel