ADC12062EVAL National Semiconductor, ADC12062EVAL Datasheet - Page 10

• Manufacturer Part Number: ADC12062EVAL
• Description: BOARD EVALUATION FOR ADC12062
• Manufacturer: National Semiconductor

Specifications of ADC12062EVAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC12062EVAL

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Pin Descriptions
PD
V
V
V
TEST
Functional Description
The ADC12062 performs a 12-bit analog-to-digital conver-
sion using a 3 step flash technique. The first flash deter-
mines the six most significant bits, the second flash gener-
ates four more bits, and the final flash resolves the two least
significant bits. Figure 4 shows the major functional blocks of
the converter. It consists of a 2
resistor ladder with two different resolution voltage spans, a
sample/hold capacitor, a 4-bit flash converter with front end
multiplexer, a digitally corrected DAC, and a capacitive volt-
age divider.
The resistor string near the center of the block diagram in
Figure 4 generates the 6-bit and 10-bit reference voltages for
the first two conversions. Each of the 16 resistors at the
bottom of the string is equal to 1/1024 of the total string
resistance. These resistors form the LSB Ladder (The
weight of each resistor on the LSB ladder is actually equiva-
lent to four 12-bit LSBs. It is called the LSB ladder because
it has the highest resolution of all the ladders in the con-
verter) and have a voltage drop of 1/1024 of the total refer-
ence voltage (V
remaining resistors form the MSB Ladder. It is comprised of
eight groups of eight resistors each connected in series (the
lowest MSB ladder resistor is actually the entire LSB ladder).
Each MSB Ladder section has
voltage across it. Within a given MSB ladder section, each of
the eight MSB resistors has 1/64 of the total reference
voltage across it. Tap points are found between all of the
REF+(FORCE)
REF+(SENSE)
REF
/16
, V
, V
sion is initiated by the falling edge of this
control input (when CS is low).
This is the Power Down control input. This
pin should be held high for normal operation.
When this pin is pulled low, the device goes
into a low power standby mode.
These are the positive and negative voltage
reference force inputs, respectively. See
Section 4, REFERENCE INPUTS, for more
information.
These are the positive and negative voltage
reference sense pins, respectively. See Sec-
tion 4, REFERENCE INPUTS, for more
information.
This pin should be bypassed to AGND with a
0.1 µF ceramic capacitor.
This pin should be tied to DV
REF+
REF−(FORCE)
REF−(SENSE)
− V
REF−
(Continued)
) across each of them. The
1
⁄
2
1
⁄
-bit Voltage Estimator, a
8
of the total reference
CC
.
10
resistors in both the MSB and LSB ladders. The Comparator
MultipIexer can connect any of these tap points, in two
adjacent groups of eight, to the sixteen comparators shown
at the right of Figure 4 . This function provides the necessary
reference voltages to the comparators during the first two
flash conversions.
The six comparators, seven-resistor string (Estimator DAC
ladder), and Estimator Decoder at the left of Figure 4 form
the Voltage Estimator. The Estimator DAC, connected be-
tween V
for the six Voltage Estimator comparators. The comparators
perform a very low resoIution A/D conversion to obtain an
“estimate” of the input voltage. This estimate is used to
control the placement of the Comparator Multiplexer, con-
necting the appropriate MSB ladder section to the sixteen
flash comparators. A total of only 22 comparators (6 in the
Voltage Estimator and 16 in the flash converter) is required
to quantize the input to 6 bits, instead of the 64 that would be
required using a traditional 6-bit flash.
Prior to a conversion, the Sample/Hold switch is closed,
allowing the voltage on the S/H capacitor to track the input
voItage. Switch 1 is in position 1. A conversion begins by
opening the Sample/Hold switch and latching the output of
the Voltage Estimator. The estimator decoder then selects
two adjacent banks of tap points aIong the MSB ladder.
These sixteen tap points are then connected to the sixteen
flash converters. For exampIe, if the input voltage is between
5/16 and 7/16 of V
decoder instructs the comparator multiplexer to select the
sixteen tap points between 2/8 and 4/8 (4/16 and 8/16) of
V
first flash conversion is now performed, producing the first 6
MSBs of data.
At this point, Voltage Estimator errors as large as 1/16 of
V
to ladder voltages that extend beyond the range specified by
the Voltage Estimator. For example, if (7/16)V
(9/16)V
tap points below (9/16)V
decoded by the estimator decoder to “10”. The 16 compara-
tors will be placed on the MSB ladder tap points between
(
matically cancel a Voltage Estimator error of up to 256 LSBs.
If the first flash conversion determines that the input voltage
is between (
Estimator’s output code will be corrected by subtracting “1”,
resulting in a corrected value of “01” for the first two MSBs.
If the first flash conversion determines that the input voltage
is between (4/8)V
estimator’s output code is unchanged.
3
REF
REF
⁄
8
)V
REF
will be corrected since the comparators are connected
and connects them to the sixteen comparators. The
REF
REF+
and (
, the Voltage Estimator’s comparators tied to the
3
⁄
and V
8
5
)V
⁄
8
)V
REF
REF
REF
REF
REF−
and ((4/8)V
(V
. This overlap of (1/16)V
− LSB/2) and (
REF
REF
, generates the reference voltages
will output “1”s (000111). This is
= V
REF+
REF
− V
− LSB/2), the Voltage
5
⁄
8
REF−
)V
REF
), the estimator
REF
, the voltage
REF
will auto-
<
V
IN
<