M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 59

• Manufacturer Part Number: M5249C3
• Description: KIT EVAL FOR M5249 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5249C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5249
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MCF5249
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The MCF5249 microprocessor has eight external interrupt request lines INT[7:0], all of which are
multiplexed with other functions. The interrupt controller is capable of providing up to 32 interrupt
sources. These sources are:
All external interrupt inputs are edge sensitive. The active level is programmable. An interrupt request
must be held valid until an IACK cycle starts to guarantee correct processing. Each interrupt input can have
it’s priority programmed by setting the xIPL[2:0] bits in the Interrupt Control Registers.
The M5249C3 hardware uses INT7 to support the ABORT function using the ABORT switch (S2). This
switch is used to force an interrupt (level 7, priority 3) if the user's program execution should be aborted
without issuing a RESET (refer to
on ABORT). Since the ABORT switch is not capable of generating a vector in response to a level seven
interrupt acknowledge from the processor, the dBUG programs this interrupt request for autovector mode.
Refer to MCF5249 User’s Manual for more information about the interrupt controller.
3.1.7
The MCF5249 processor has 96-KBtyes of internal memory which may be programmed as data or
instruction memory. This memory is mapped to 0x20000000 and configured as data space but is not used
by the dBUG monitor except during system initialisation. After system initialisation is complete, the
internal memory is available to the user. The memory is relocatable to any 32-KByte boundary.
3.1.8
The memory and I/O resources of the M5249C3 hardware are divided into two groups, MCF5249 internal
and external resources. All the I/O registers are memory mapped.
The MCF5249 processor has built in logic and up to four chip-select pins (CS[3:0]) which are used to
enable external memory and I/O devices. In addition there are SDRAS and SDCAS lines available for
controlling SDRAMs. There are registers to specify the address range, type of access and the method of
TA generation for each chip-select. These registers are programmed by the dBUG monitor to map the
external memory and I/O devices.
Freescale Semiconductor
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External interrupt signals INT[7:0]
Software watchdog timer module
Two general purpose timer modules
UART module
I
Audio interface modules
DMA module
QSPI module
2
C module
Internal SRAM
The MCF5249 Registers and Memory Map
No interrupt sources should have the same level and priority as another.
Programming two interrupt sources with the same level and priority can
result in undefined operation.
Chapter 2, “Using the Monitor/Debug Firmware,”
M5249C3 User’s Manual, Rev. 1
NOTE
Hardware Description and Reconfiguration
for more information
3-3