M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 61

• Manufacturer Part Number: M5249C3
• Description: KIT EVAL FOR M5249 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5249C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5249
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MCF5249
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

initialisation routine then programs the chip-select logic, locates the Flash ROM to start at $FFE00000
and configures the rest of the internal and external peripherals.
3.1.10
The processor starts a bus cycle by asserting CSx with the other control signals. The processor then waits
for a transfer acknowledgment (TA) either from within (Auto acknowledge - AA mode) or from the
externally addressed device before it can complete the bus cycle. TA is used to indicate the completion of
the bus cycle. It also allows devices with different access times to communicate with the processor
properly (i.e. asynchronously) like the Ethernet controller (U4). The MCF5249 processor, as part of the
chip-select logic, has a built-in mechanism to generate TA for all external devices which do not have the
capability to generate this signal. For example the Flash ROM cannot generate a TA.signal. The chip-select
logic is programmed by the dBUG ROM Monitor to generate TA internally after a pre-programmed
number of wait states. In order to support future expansion of the M5249C3 board, the TA input of the
processor is also connected to the Processor Expansion Bus (J5, pin 66). This allows any expansion boards
to assert this line to provide a TA signal to the processor. On the expansion boards this signal should be
generated through an open collector buffer with no pull-up resistor; a pull-up resistor is included on this
board. All TA signals from expansion boards should be connected to this line.
3.1.11
The Flash ROM and SDRAM on the board may require some adjustments to the cycle time of the
processor to make them compatible with the processor’s external bus speed. To extend the CPU bus cycles
for the slower devices, the chip-select logic of the MCF5249 processor can be programmed to generate an
internal TA after a given number of wait states. Refer to
of the memory and refer to the manufacturers specification for wait state requirements of the SDRAM and
Flash ROM.
3.1.12
The M5249C3 has one 64-MBit device on the board, in a 16-bit wide data bus configuration. The
MCF5249 processor supports one bank of SDRAM, which on this board is represented by SDRAM
device, (U7). These are connected to the MCF5249 to provide 4Mx16 of memory.
3.1.13
There is one 2-MByte Flash ROM on the M5249C3, (U6).
The board is shipped with one AMD Am29LV160DB, 2-MByte Flash ROM. The first 256-Kbytes of the
Flash contains the ROM Monitor firmware dBUG. The remaining Flash memory is available to the user
via use of jumper 12.
The MCF5249 chip-select logic can be programmed to generate the TA for CS0 signal after a certain
number of wait states (i.e. auto acknowledge mode). The dBUG monitor programs this parameter to be
six wait-states.
Freescale Semiconductor
TA Generation
Wait State Generator
SDRAM
Flash ROM
M5249C3 User’s Manual, Rev. 1
Table 3-1
for information about the address space
Hardware Description and Reconfiguration
3-5