C8051F124-TB Silicon Laboratories Inc, C8051F124-TB Datasheet - Page 215
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C8051F124-TB
Manufacturer Part Number
C8051F124-TB
Description
BOARD PROTOTYPING W/C8051F124
Manufacturer
Silicon Laboratories Inc
Specifications of C8051F124-TB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
CHWREN CHRDEN CHPFEN CHFLSH
R/W
Bit7
CHWREN: Cache Write Enable.
This bit enables the processor to write to the cache memory.
0: Cache contents are not allowed to change, except during Flash writes/erasures or cache
locks.
1: Writes to cache memory are allowed.
CHRDEN: Cache Read Enable.
This bit enables the processor to read instructions from the cache memory.
0: All instruction data comes from Flash memory or the prefetch engine.
1: Instruction data is obtained from cache (when available).
CHPFEN: Cache Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
CHFLSH: Cache Flush.
When written to a ‘1’, this bit clears the cache contents. This bit always reads ‘0’.
CHRETI: Cache RETI Destination Enable.
This bit enables the destination of a RETI address to be cached.
0: Destinations of RETI instructions will not be cached.
1: RETI destinations will be cached.
CHISR: Cache ISR Enable.
This bit allows instructions which are part of an Interrupt Service Rountine (ISR) to be
cached.
0: Instructions in ISRs will not be loaded into cache memory.
1: Instructions in ISRs can be cached.
CHMOVC: Cache MOVC Enable.
This bit allows data requested by a MOVC instruction to be loaded into the cache memory.
0: Data requested by MOVC instructions will not be cached.
1: Data requested by MOVC instructions will be loaded into cache memory.
CHBLKW: Block Write Enable.
This bit allows block writes to Flash memory from software.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of four (for code space writes) or two (for scratchpad
writes).
R/W
Bit6
SFR Definition 16.1. CCH0CN: Cache Control
R/W
Bit5
R/W
Bit4
CHRETI
Rev. 1.4
R/W
Bit3
C8051F120/1/2/3/4/5/6/7
CHISR
R/W
Bit2
CHMOVC CHBLKW 11100110
C8051F130/1/2/3
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xA1
F
Reset Value
215
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