HSP-EVAL Intersil, HSP-EVAL Datasheet - Page 5

• Manufacturer Part Number: HSP-EVAL
• Description: EVALUATION BOARD DSP MOTHER
• Manufacturer: Intersil
• Type: DSPr

Specifications of HSP-EVAL

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: HSPxx Family
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The registers driving the control and input busses may be
three-stated when it is desired to drive those busses through
the 96 Pin Input Connector or headers on the target
daughter board. The registers driving a particular bus are
three-stated by removing the respective Output Enable
jumper in the J4 Configuration Jumper Field (see
Configuration Jumper Field).
The HSP-EVAL's two 16-bit output busses can be serialized
by a 32-bit shift register for reading via the Parallel Port Bus.
The CTL Control Register governs the loading and clocking
of data out of the shift register. The mapping of this register
to the output busses is shown in Table 8.
TABLE 5. SIGNAL ASSIGNMENTS FOR 50 POSITION
NUMBER
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
CONTROL CONNECTOR J3
J3A SIGNAL
MNEMONIC
IN3_11
IN3_13
IN3_15
CTL10
CTL12
CTL14
IN3_0
IN3_2
IN3_4
IN3_6
IN3_9
CTL1
CTL3
CTL5
CTL7
CTL8
GND
GND
GND
GND
GND
GND
GND
N.C.
N.C.
5
J3B SIGNAL
MNEMONIC
IN3_10
IN3_12
IN3_14
CTL11
CTL13
CTL15
IN3_1
IN3_3
IN3_5
IN3_7
IN3_8
CTL0
CTL2
CTL4
CTL6
CTL9
GND
GND
GND
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
HSP-EVAL
Down Loading Data via Parallel Port
Interface
The four “logical” control and input registers are down loaded
by a series of single byte writes to the to the Parallel Port
Interface. The Parallel Port Interface consists of two
decoders, an 8-bit address register, and an 8-bit holding
register. The on-board registers are down loaded by first
writing data to the Parallel Port Interface's holding register
followed by two writes to the Interface's Address Register. By
writing the address register, data in the holding register is
loaded into one of the eight registers on-board the HSP-
EVAL. The address register specifies the particular register
for loading, as well as the board address of the HSP-EVAL
targeted for the data download. The HSP-EVAL board
address is selected in the J4 Jumper Field (see
Configuration Jumper Field Section), and the memory map
for the 8 data registers is shown in Table 7. The bit map for
the Parallel Port Interface’s Address Register is given in
Table 9.
The Parallel Port Interface's address and holding registers
are loaded with data from the PCD0-7 data lines of the
Parallel Port Bus by a “low” to “high” transition on the
appropriate bus control line. Specifically, the Interface's
Address Register is loaded with data when a “low” to “high”
transition occurs on the PCWR0 line of the Parallel Port Bus,
and the holding register is loaded by a like transition on the
PCWR1 line. The mapping of the Parallel Port Bus signals
mentioned above to the PC's parallel port is given in Table 6.
NOTE: BM PC compatible parallel port signals are shown in
TABLE 6. SIGNAL MAPPING SFOR 27 PIN SHROUDED
NUMBER
parenthesis.
PIN
10
11
12
13
1
2
3
4
5
6
7
8
9
HEADER J5
N.C.
PCD0 (D0)
PCD1 (D1)
PCD2 (D2)
PCD3 (D3)
PCD4 (D4)
PCD5 (D5)
PCD6 (D6)
PCD7 (D7)
N.C.
PCRD0 (BUSY)
PCRD2 (PAPER
END)
PCRD1 (SELECT)
J6A SIGNAL
MNEMONIC
N.C.
N.C.
PCWR0 (INIT
PRINTER)
PCWR1 (SELECT
IN)
GND
GND
GND
GND
GND
GND
GND
GND
GND
J6B SIGNAL
MNEMONIC