DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 73

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6.0 Electrical Specifications
6.2 Reset Timing
V
T1
T2
T3
T4
T5
Note 1: Guaranteed by design. Not tested.
Note 2: It is recommended to use external pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time con-
stants in order to latch-in the proper value prior to the pin transitioning to an output driver. Unless otherwise noted in the Pin Description section all
external pull-up or pull-down resistors are recommended to be 2k
Parameter
DD
3.3V (I/O if applicable)
Latch-In of Hardware
1.8V (core, analog),
2.5V (I/O, analog),
Configuration Pins
CLK_TO_MAC
Reference clock settle time The reference clock must be stable af-
Hardware RESET Pulse
Width
Post RESET Stabilization
time prior to MDC preamble
for register accesses
External pull configuration
latch-in time from the deas-
sertion of RESET
CLK_TO_MAC Output Sta-
bilization Time
CLK_IN
RESET
MDC
Description
(Continued)
ter the last power supply voltage has
settled and before RESET is deas-
serted. (Note 1)
Pins VDD_SEL and CLK_MAC_EN
are latched in during this time.
Power supply voltages and the refer-
ence clock (CLK_IN) have to be sta-
ble.
MDIO is pulled high for 32-bit serial
management initialization.
Hardware Configuration Pins are de-
scribed in the Pin Description section.
Reset includes external hardware and
internal software through registers.
(Note 2)
If enabled, the CLK_TO_MAC output,
being independent of RESET, power-
down mode and isolation mode, is
available after power-up.
CLK_TO_MAC is a buffered output
CLK_IN. (Note 1)
T1
73
T5
Notes
T2
T3
T4
0 + T1
Min
150
20
20
0
32 clocks
Typ
Max
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Units
ms
ms
s
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