HW-XGI-SCLK-G Xilinx Inc, HW-XGI-SCLK-G Datasheet - Page 9

• Manufacturer Part Number: HW-XGI-SCLK-G
• Description: MODULE SUPER CLOCK
• Manufacturer: Xilinx Inc

Specifications of HW-XGI-SCLK-G

• Accessory Type: Clock
• For Use With/related Products: ML423, ML521, ML523, ML525
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Xilinx Generic Interface (XGI) SuperClock Module
UG091 (v1.1) March 2, 2007
R
The SuperClock module generates stable, low phase noise, 100Ω differentially terminated
reference clock outputs utilizing a crystal-to-3.3V LVPECL frequency synthesizer
(843001AG-22) from Integrated Device Technology (IDT)
interface provides a platform capable of supporting two selectable clock rate outputs with
a voltage-controlled oscillator (VCO) range of 490 MHz to 640 MHz. Control is provided
through onboard switch selection (SW1) or the 2 x 32 external board interface connector
(J1) when connected to a host board. A list of selectable I/O associations is presented in
Table
through the 1 x 32 external board interface connector (J11), and is regulated onboard at
3.3V DC.
The synthesizer rate is determined using the fundamental crystal or externally supplied
test clock (TEST_CLK) frequency
setting of M0, M1, and M2
dividing the synthesizer rate by the output divider selection of N0, N1, and N2
page
coverage gaps as shown in
corresponding configuration selections. Coupled to the output differential pair is an 8543,
low skew, 1-to-4 differential fan-out buffer that is used as a clock splitter and PECL-to-
LVDS driver. The fan-out buffer configuration is preselected.
Table 1: Selectable I/O Associations
N0
N1
N2
M0
M1
M2
SEL0
SEL1
MR
REF_OE
Signal
Name
10). Full range output clock capability is from 49 MHz to 640 MHz (with minimal
1. Power is supplied externally at 5V DC from a stand-alone supply, or optionally
Output divider select. Default is /4.
Feedback divider select. Default is /32.
Input clock source select.
Master reset.
Reference clock OE.
www.xilinx.com
(Table 3, page
Figure 3, page
Function
(Table 2, page
10). The output clock rate is then determined by
11). LEDs on the board indicate the
10) multiplied by the feedback divider
SW1, pin 1
SW1, pin 2
SW1, pin 3
SW1, pin 4
SW1, pin 5
SW1, pin 6
SW1, pin 7
SW1, pin 8
SW2
J13
[Ref
Operation
3]. The dual-crystal
Functional Description
J1, pin 8
J1, pin 10
J1, pin 12
J1, pin 14
J1, pin 16
J1, pin 18
J1, pin 20
J1, pin 22
J1, pin 24
N/A
(Table 4,
DS1
DS3
DS2
DS8
DS6
DS7
DS4
DS5
N/A
N/A
LED
9