ICL7104-14CPL Intersil, ICL7104-14CPL Datasheet - Page 12

• Manufacturer Part Number: ICL7104-14CPL
• Description: 14 BIT A/D CONVERTER
• Manufacturer: Intersil

Specifications of ICL7104-14CPL

• Rohs Status: RoHS non-compliant
• Other names: NT5018

Auto-Zero and Reference Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system, a large capacitor giving less noise.
The reference capacitor should be large enough such that
stray capacitance to ground from its nodes is negligible.
NOTE: When gain is used in the buffer amplifier the reference
capacitor should be substantially larger than the auto-zero capacitor.
As a rule of thumb, the reference capacitor should be approximately
the gain times the value of the auto-zero capacitor. The dielectric
absorption of the reference cap and auto-zero cap are only important
at power-on or when the circuit is recovering from an overload. Thus,
smaller or cheaper caps can be used here if accurate readings are
not required for the first few seconds of recovery.
Reference Voltage
The analog input required to generate a full scale output is
V
The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. The resolution of
the ICL7104 at 16 bits is one part in 65536, or 15.26ppm.
Thus, if the reference has a temperature coefficient of
50ppm/C (on board reference) a temperature change of 1/3C
will introduce a one-bit absolute error. For this reason, it is rec-
ommended that an external high quality reference be used
where the ambient temperature is not controlled or where
high-accuracy absolute measurements are being made.
Detailed Description
DIGITAL SECTION
The digital section includes the clock oscillator circuit, a
16-bit or 14-bit binary counter with output latches and TTL-
compatible three-state output drivers, polarity, over-range
IN
ICL7104-16 POL
ICL7104-14
= 2V
REF
.
HBEN
O/R
POL
B16
TABLE 5. THREE-STATE BYTE FORMATS AND ENABLE PINS
B15
O/R
B14
B14
B13
B13
MBEN
HBEN
B12
B12
ICL7104
B11
B11
12
and control logic and UART handshake logic, as shown in
the Block Diagram Figure 9 (16-bit version shown).
Throughout this description, logic levels will be referred to as
“low” or “high”. The actual logic levels are defined under
“ICL7104 Electrical Specification”. For minimum power con-
sumption, all inputs should swing from GND (low) to V+
(high). Inputs driven from TTL gates should have 3 - 5kΩ
pullup resistors added for maximum noise immunity.
MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is connected to GND or left
open (this input is provided with a pulldown resistor to
ensure a low level when the pin is left open), the converter is
in its “Direct” output mode, where the output data is directly
accessible under the control of the chip and byte enable
inputs. When the MODE input is pulsed high, the converter
enters the UART handshake mode and outputs the data in
three bytes for the 7104-16 or two bytes for the 7104-14 then
returns to “direct” mode. When the MODE input is left high,
the converter will output data in the handshake mode at the
end of every conversion cycle. (See section entitled “Hand-
shake Mode” for further details).
STATUS Output
During a conversion cycle, the STATUS output goes high at
the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion has
been stored in the output latches. See Figure 8 for details of
this timing. This signal may be used as a “data valid” flag
(data never changes while STATUS is low) to drive inter-
rupts, or for monitoring the status of the converter.
B10
B10
CE/LD
B9
B9
B8
B8
B7
B7
B6
B6
B5
B5
LBEN
LBEN
B4
B4
B3
B3
B2
B2
B1
B1