CA3524E Intersil, CA3524E Datasheet - Page 7

• Manufacturer Part Number: CA3524E
• Description: REGUL. PULSE WIDTH MODULATOR
• Manufacturer: Intersil

Specifications of CA3524E

• Rohs Status: RoHS non-compliant
• Other names: CA3524

Circuit Description
Voltage Reference Section
The CAl524 series contains an internal series voltage regu-
lator employing a zener reference to provide a nominal 5-volt
output, which is used to bias all internal timing and control
circuitry. The output of this regulator is available at terminal
l6 and is capable of supplying up to 50mA output current.
Figure 1 shows the temperature variation of the reference
voltage with supply voltages of 8V to 40V and load currents
up to 20mA. Load regulation and line regulation curves are
shown in Figures 2 and 3, respectively.
FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
FIGURE 3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
5.02
5.00
4.98
4.96
-60 -40 -20
5.1
4.9
4.7
4.5
4.3
4.1
3.9
3.7
3.5
8
7
6
5
4
3
2
1
0
OF AMBIENT TEMPERATURE
OF REFERENCE OUTPUT CURRENT
OF SUPPLY VOLTAGE
0
0
AMBIENT TEMPERATURE (
TA = +25oC
V+ = 20V
TA = +25oC
REFERENCE OUTPUT CURRENT (mA)
8
0
10
16
20
SUPPLY VOLTAGE, V+ (V)
24
40 60 80 100 120 140
20
32
40 48
30
o
C)
V+ = 20V
56 64
40
CA1524, CA2524, CA3524
V+ = 8V
V+ = 40V, I
V+ = 20V, I
V+ = 40V, I
V+ = 8V, I
V+ = 20V, I
V+ = 8V, I
V+ = 40V
72
L
L
L
L
L
L
80
= 0mA
= 20mA
= 0mA
= 0mA
= 20mA
= 20mA
7
Osclllator Section
Transistors Q42, Q43 and Q44, in conjunction with an
external resistor R
into an external capacitor C
at terminal 7. The ramp voltage has a value that ranges from
0.6V to 3.5V and is used as the reference for the comparator
in the device. The charging current is equal to (5-2V
approximately 3.6/R
30pA to 2mA by varying R
mines the pulse width of the oscillator output pulse at termi-
nal 3. This pulse has a practical range of 0.5 s to 5 s for a
capacitor range of 0.001 to 0.1 F. The pulse has two internal
uses: as a dead-time control of blanking pulse to the output
stages to assure that both outputs cannot be on simulta-
neously and as a trigger pulse to the internal flip-flop which
controls the switching of the output between the two output
channels. The output dead-time relationship is shown in Fig-
ure 4. Pulse widths less than 0.5 s may allow false trigger-
ing of one output by removing the blanking pulse prior to a
stable state in the flip-flop.
If a small value of C
further expanded by the addition of a shunt capacitor in the
order of 100pF but no greater than 1000pF, from terminal 3
to ground. When the oscillator output pulse is used as a sync
input to an oscilloscope, the cable and input capacitances
may increase the pulse width slightly. A 2-K
terminal 3 will usually provide sufficient decoupling of the
cable. The upper limit of the pulse width is determined by the
maximum duty cycle acceptable.
The oscillator period is determined by R
approximate value of t = R
capacitances, should be avoided in connecting R
their respective terminals. Figure 5 provides curves for
selecting these values for a wide range of oscillator periods.
For series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle with
the output stage frequency the same as the oscillator
frequency. Since the outputs are separate, push-pull and
flyback applications are possible. The flip-flop divides the
frequency such that the duty cycle of each output is 0-45%
and the overall frequency is half that of the oscillator. Curves
F, and t is in s. Excess lead lengths, which produce stray
FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A
100
1.0
0.1
10
0.0001
FUNCTION OF TIMING CAPACITOR VALUE
T
V+ = 8V - 40V
T
A
, establishes a constant charging current
T
= +25
T
0.001
TIMING CAPACITOR, C
and should be kept within the range of
must be used, the pulse width can be
o
C
T
T
. The discharge time of C
T
C
to provide a linear ramp voltage
T
, where R
0.01
T
T
0.1
is in ohms, C
( F)
T
and C
T
resistor at
T
1.0
and C
BE
, with an
T
)/R
deter-
T
is in
T
T
or
to