74ALVC16373 Fairchild Semiconductor, 74ALVC16373 Datasheet
74ALVC16373
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74ALVC16373 Summary of contents
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... Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The 74ALVC16373 is designed for low voltage (1.1V to 3.6V) V applications with I/O compatibility up to 3.6V. CC ...
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Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Latch Enable Input n I –I Inputs –O Outputs 0 ...
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... Functional Description The 74ALVC16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LE ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 5) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter V CC Min Propagation Delay PHL PLH 1.3 Bus to Bus Propagation Delay PHL PLH 1 Bus Output Enable Time 1.3 PZL PZH t ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3.3V 0. FIGURE 2. Waveform for Inverting and ...
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Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...