74ALVC16374 Fairchild Semiconductor, 74ALVC16374 Datasheet
74ALVC16374
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74ALVC16374 Summary of contents
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... The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The 74ALVC16374 is designed for low voltage (1.65V to 3.6V) V applications with I/O compatibility up to 3.6V. CC ...
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Logic Symbol Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Clock Pulse Input n I –I Inputs –O ...
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... Functional Description The 74ALVC16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte func- tioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 5) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter V CC Min f Maximum Clock Frequency 250 MAX Propagation Delay PHL PLH 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit Symbol 3. FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and ...
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Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...