74lvc32245a NXP Semiconductors, 74lvc32245a Datasheet

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74lvc32245a

Manufacturer Part Number
74lvc32245a
Description
32-bit Bus Transceiver With Direction Pin; 5 V Tolerant; 3-state
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
3. Ordering information
Table 1.
Type number
74LVC32245AEC
Ordering information
Package
Temperature range Name
40 C to +85 C
The 74LVC32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible
outputs in both send and receive directions. The device features four output enable (nOE)
inputs for easy cascading and four send/receive (nDIR) inputs for direction control.
Pin nOE controls the outputs so that the buses are effectively isolated.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
To ensure the high-impedance state during power-up or power-down, pin nOE should be
tied to V
the current-sinking capability of the driver.
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74LVC32245A
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Rev. 01 — 20 August 2007
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when V
Complies with JEDEC standard JESD8-B / JESD36
ESD protection:
Specified from 40 C to +85 C
Packaged in plastic fine-pitch ball grid array package
N
N
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CC
through a pull-up resistor; the minimum value of the resistor is determined by
LFBGA96 plastic low profile fine-pitch ball grid array package;
CC
Description
96 balls; body 13.5
= 0 V
5.5
1.05 mm
Product data sheet
Version
SOT536-1

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74lvc32245a Summary of contents

Page 1

... Rev. 01 — 20 August 2007 1. General description The 74LVC32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features four output enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction control. ...

Page 2

... T3 3OE J4 4A0 N5 3B0 J2 4A1 N6 3B1 J1 4A2 P5 3B2 K2 4A3 P6 3B3 K1 4A4 R5 3B4 L2 4A5 R6 3B5 L1 4A6 T6 3B6 M2 4A7 T5 3B7 M1 Rev. 01 — 20 August 2007 74LVC32245A 2OE H4 2B0 E2 2B1 E1 2B2 F2 2B3 F1 2B4 G2 2B5 G1 2B6 H1 2B7 H2 4OE T4 4B0 N2 4B1 N1 4B2 P2 4B3 P1 4B4 R2 4B5 R1 4B6 T1 4B7 T2 mna476 © ...

Page 3

... J2, J1, K2, K1, L2, L1, M2, M1 N5, N6, P5, P6, R5, R6, T6, T5 N2, N1, P2, P1, R2, R1, T1, T2 B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3, M4, N3, N4, R3, R4 C3, C4, F3, F4, L3, L4, P3, P4 Output nAn inputs Z Rev. 01 — 20 August 2007 74LVC32245A mna475 3A3 3A5 3A7 4A1 4A3 4A5 4A6 3A2 3A4 3A6 ...

Page 4

... +85 C amb Conditions for maximum speed performance for low-voltage applications output HIGH or LOW state output 3-state in free air Rev. 01 — 20 August 2007 74LVC32245A Min Max Unit 0.5 +6 [1] 0.5 +6 [2] 0 0.5 ...

Page 5

... GND per input pin 0 GND GND 3.3 V (unless stated otherwise) and T CC Rev. 01 — 20 August 2007 74LVC32245A V (V) Min Typ CC 1 2.7 to 3.6 2.0 1.2 - 2.7 to 3.6 - 2.7 to 3 2.7 V 0.5 CC 3.0 V 0.6 CC 3.0 V ...

Page 6

... Figure 4 per buffer GND and V = 1.2 V, 2.7 V, and 3.3 V respectively. amb where nAn, nBn V M input GND t PHL V OH nBn, nAn V M output V OL Rev. 01 — 20 August 2007 74LVC32245A 5. V (V) Min Typ CC [2] 1.2 - 13.0 2.7 1.0 2.7 3.0 to 3.6 1.0 2.2 [2] 1.2 - 15.0 2.7 1.5 3.6 3.0 to 3.6 1.0 2.8 [2] 1.2 - 11.0 2.7 1.5 3.4 3.0 to 3.6 1 ...

Page 7

... V tolerant; 3-state GND t PLZ PHZ GND outputs enabled 2.7 V. 2.7 V. Rev. 01 — 20 August 2007 74LVC32245A t PZL PZH V M outputs outputs enabled disabled mna362 © NXP B.V. 2007. All rights reserved ...

Page 8

... DUT R T Load 2 2 Rev. 01 — 20 August 2007 74LVC32245A EXT 001aae331 of the pulse generator EXT PLH PHL ...

Page 9

... 5.6 13.6 0 0.15 5.4 13.4 REFERENCES JEDEC JEITA Rev. 01 — 20 August 2007 74LVC32245A detail 0.1 0.1 0.2 EUROPEAN PROJECTION SOT536-1 ISSUE DATE 00-03-04 03-02-05 © NXP B.V. 2007. All rights reserved ...

Page 10

... Revision history Document ID Release date 74LVC32245A_1 20070820 74LVC32245A_1 Product data sheet 32-bit bus transceiver with direction pin tolerant; 3-state Data sheet status Change notice Product data sheet - Rev. 01 — 20 August 2007 74LVC32245A Supersedes - © NXP B.V. 2007. All rights reserved ...

Page 11

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 20 August 2007 74LVC32245A © NXP B.V. 2007. All rights reserved ...

Page 12

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC32245A All rights reserved. Date of release: 20 August 2007 Document identifier: 74LVC32245A_1 ...

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