CY28346 Cypress Semiconductor, CY28346 Datasheet
CY28346
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CY28346 Summary of contents
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... PCI(0:6) PCI_F(0:2) 48M USB 48M DOT 66B0/3V66_2 66B1/3V66_3 66B2/3V66_4 66IN/3V66_5 66B[0:2]/3V66[2:4] 66IN/3V66-5 • 3901 North First Street • San Jose CY28346 PCI_FPCI REF USB/ DOT 66IN/2 14.318M 48M 66IN/2 14.318M 48M 66IN/2 14.318M 48M 66IN/2 14.318M 48M 33 M 14.318M ...
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... IREF. This pin should also be returned to device PWR Analog Power Input. Used for phase-locked loops (PLLs) and internal analog circuits also specifically used to detect and determine when power acceptable level to enable the device to operate. CY28346 Description Clock. IN Page ...
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... Read and Write control bit. CPUT/C1 Output Control enabled disable HIGH and CPUC1 disables LOW. This is a Read and Write control bit. CPUT/C0 Output Control enabled disable HIGH and CPUC0 disables LOW. This is a Read and Write control bit. CY28346 Description Page ...
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... Control LSB Reserved. Set = 48MDOT Edge Rate Control. When set to 1, the edge is slowed by 15 Reserved. Set = USB edge rate control. When set to 1, the edge is slowed by 15%. Document #: 38-07331 Rev. *B Description Description Description Description CY28346 Page ...
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... R and N register mux selection and N values come from the ROM data is loaded 0 0 from DAF (SMBus) registers. Note: 4. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored. Document #: 38-07331 Rev. *B [4] (all bits are Read-only) Description Description Description Description CY28346 Page ...
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... The following diagram shows lumped test load configurations for the differential Host Clock Outputs Figure 1. 1.0V Test Load Termination T PCB 2pF T PCB 2pF Figure 2. 0.7V Test Load Termination CY28346 SS0 Spread Mode Spread% 0 Down +0.00, –0.25 1 Down +0.00, –0.50 0 Down +0.00, –0.75 1 Down +0.00, – ...
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... Vop (see Figure 4). 3. Series resistance in the buffer circuit – Ros (see Figure 4). 4. Current accuracy at given configuration into nominal test load for given configuration. Iout 0V Figure 4. Buffer Characteristics Min. 3000 (recommended) N/A CY28346 Output under Test Probe Load Cap - Slope ~ 1/R 0 1.2V Vout Max. ...
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... The measurements were taken at 1.5V. 3V66 to PCI Un-Buffered Clock Skew Figure 8 shows the timing relationship between 3V66(0:5) and PCI(0:6) and PCI_F(0:2) when configured to run in the unbuf- fered mode. Figure 6. 66IN to 66B(0:2) Output Delay Figure CY28346 Output Current Voh @ Z Ioh = 4*Iref 1. Ioh = 6*Iref 0. ...
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... CPUC clock cycles. Three-state Control of CPU Clocks Clarification During CPU_STP# and PD# modes, CPU clock outputs may be set to driven or undriven (tri-state) by setting the corre- sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1. Figure 9. CPU_STP# Assertion Waveform CY28346 Page ...
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... Iref x2 0 Iref x2 1 Running Running 0 Hi-Z 1 Hi-Z 0 Hi-Z 1 Running Running 0 Iref x6 1 Hi-Z 0 Hi-Z 1 Running Running 0 Hi-Z 1 Hi-Z 0 Hi-Z CY28346 Non-Stop CPUT Non-Stop CPUC CPUC Running Running Iref x6 Running Running LOW Iref x2 LOW Iref x2 Running Running Hi-Z Running Running Hi-Z Hi-Z Hi-Z Hi-Z Running Running Iref x6 Running Running Hi-Z Hi-Z Hi-Z Hi-Z Running ...
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... PD# – Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ms. t setup Figure 11. PCI_STP# Assertion Waveform t setup Figure 12. PCI_STP# Deassertion Waveform CY28346 Page ...
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... CPU# 133MHz 3V66 66In USB 48MHz REF 14.318MHz Figure 13. power-down Assertion Timing Waveforms Figure – Buffered Mode PWRDWN# CPUT(0:2) 133MHz CPUC(0:2) 133MHz PCI 33MHz 3V66 USB 48MHz REF 14.318MHz Figure 14. Power-down Assertion Timing Waveforms –Unbuffered Mode Document #: 38-07331 Rev. *B CY28346 Page ...
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... USB 48MHz REF 14.318MHz Figure 15. Power-down Deassertion Timing Waveforms – Buffered Mode Table 8. PD# Functionality PD# DRCG 1 66M 0 LOW Document #: 38-07331 Rev. *B 30uS min <1.8mS 400uS max 66CLK (0:2) PCI_F/PCI 66Input 66Input/2 LOW LOW CY28346 PCI USB/DOT 66Input/2 48M LOW LOW Page ...
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... V 0. 0. 10.0 10.0 500 500 7.35 7.65 4.85 5.1 100 100 = 0.175V 0.525V CY28346 Min. Max. – Inom Inom –12% + 12% Inom Inom Max. Unit 280 mA Note Unit Notes % 9, 10 12, 13 ...
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... CY28346 133 MHz 200 MHz Max. Min. Max. Unit 150 150 ps 700 175 700 ps 20% 20% 125 125 ps 125 125 ps 430 280 430 7.65 4.85 5.1 nS ...
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... CY28346 133 MHz 200 MHz Min. Max. Min. Max. Unit 0.5 2.0 0.5 2.0 ns 175 175 ps 2.5 4.5 2.5 4.5 ns 100 100 30 ...
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... MHz Min. Max. Min. Max. 1.0 10.0 1.0 10.0 1.0 10.0 1.0 10 10.0 10 0.2-0.3mS Wait for Sample Sels Delay VTT_GD# State 1 State 2 On Figure 16. VTT_PWRGD# Timing CY28346 133 MHz 200 MHz Min. Max. Min. Max. Unit 1.0 10.0 1.0 10.0 1.0 10.0 1.0 10 10.0 10 State 3 (Note A) On Max Load ...
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... VDD3.3 = Off Package Type 56-pin SSOP – Tube 56-pin SSOP – Tape and Reel 56-pin TSSOP – Tube 56-pin TSSOP – Tape and Reel 56-lead Shrunk Small Outline Package O56 CY28346 Enable Outputs S3 Normal Operation Product Flow Commercial Commercial ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28346 51-85060-B ...
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... Document Title: CY28346 Clock Synthesizer with Differential CPU Outputs Document Number: 38-07331 REV. ECN NO. Issue Date ** 111653 02/21/02 *A 113983 03/08/02 *B 122897 12/26/02 Document #: 38-07331 Rev. *B Orig. of Change Description of Change DMG New Data Sheet DMG Figure 14 changed RBI Add power up requirements to maximum ratintgs information CY28346 ...