IDT72V3650 Integrated Device Technology, IDT72V3650 Datasheet
IDT72V3650
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IDT72V3650 Summary of contents
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... WCLK/WR INPUT REGISTER RAM ARRAY 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 OUTPUT REGISTER * Q -Q (x36, x18 or x9 IDT72V3640, IDT72V3650 IDT72V3660, IDT72V3670 IDT72V3680, IDT72V3690 LD SEN OFFSET REGISTER FF/IR PAF EF/OR PAE FLAG HF LOGIC FWFT/SI PFM FSEL0 ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 DESCRIPTION: The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 words written to the FIFO do require a LOW on REN for access. The state ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 PIN DESCRIPTION (TQFP AND PBGA PACKAGES) Symbol Name I/O BM (1) Bus-Matching I BM works ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES) Symbol Name I/O SEN SEN enables serial loading of ...
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... Input Low Voltage Com’l/Ind’l — — Operating Temperature 0 — Commercial Operating Temperature -40 — Industrial = -40°C to +85°C; JEDEC JESD8-A compliant) A IDT72V3640L IDT72V3650L IDT72V3660L IDT72V3670L IDT72V3680L IDT72V3690L Commercial and Industrial ( 7-5, 10 CLK Min. Max. –1 1 – ...
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... A OE OHZ 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l (2) TQFP Only TQFP Only IDT72V3640L15 IDT72V3650L15 IDT72V3660L15 IDT72V3670L15 IDT72V3680L15 IDT72V3690L15 Max. Min. Max. Unit — 100 — 66.7 MHz (5) 6 — ...
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... Commercial IDT72V3640L6 IDT72V3650L6 IDT72V3660L6 IDT72V3670L6 IDT72V3680L6 IDT72V3690L6 Min. — 0.6 10 4.5 4.5 8 — — — — 10 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l IDT72V3640L7-5 IDT72V3650L7-5 IDT72V3660L7-5 IDT72V3670L7-5 IDT72V3680L7-5 IDT72V3690L7-5 Max. Min. Max. Unit 100 — 83 MHz 8 0 — 12 — ns — 5 — ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference ...
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... If no reads are performed after a reset, IR will go HIGH after D writes to the FIFO 1,025 writes for the IDT72V3640, 2,049 writes for the IDT72V3650, 4,097 writes for the IDT72V3660 and 8,193 writes for the IDT72V3670,16,385 writes for the IDT72V3680 and 32,769 writes for the IDT72V3690, respectively ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 TABLE 2 — DEFAULT PROGRAMMABLE FLAG OFFSETS IDT72V3640, 72V3650 LD FSEL1 FSEL0 ...
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... IDT72V3690 IDT72V3680 0 0 (1) ( (n+1) to 8,192 (n+1) to 16,384 8,193 to (16,384-(m+1)) 16,385 to (32,768-(m+1)) (16,384-m) to 16,383 (32,768-m) to 32,767 16,384 32,768 IDT72V3660 IDT72V3650 n n+1 (n+2) to 1,025 (n+2) to 2,049 1,026 to (2,049-(m+1)) 2,050 to (4,097-(m+1)) (2,049-m) to 2,048 (4,097m) to 4,096 2,049 4,097 IDT72V3690 IDT72V3680 n+1 ...
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... WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V3640 IDT72V3650 IDT72V3660 IDT72V3670 IDT72V3680 IDT72V3690 No Operation Write Memory Read Memory No Operation 4667 drw06 APRIL 6, 2006 ...
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... Bus Width 16 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES # of Bits Used: 10 bits for the IDT72V3640 11 bits for the IDT72V3650 12 bits for the IDT72V3660 13 bits for the IDT72V3670 14 bits for the IDT72V3680 15 bits for the IDT72V3690 Note: All unused bits of the LSB & MSB are don't care ...
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... WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 20 bits for the IDT72V3640, 22 bits for the IDT72V3650, 24 bits for the IDT72V3660, 26 bits for the IDT72V3670, 28 bits for the IDT72V3680 and 30 bits for the IDT72V3690. See Figure 15, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 was HIGH before setup. During this period, the internal read pointer is initialized ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 36-bit ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 not there are any words present in the FIFO memory. It also uses the Full ...
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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690 ...
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... In FWFT mode reads are performed after reset (MRS or PRS), HF will go LOW after (D-1 writes to the FIFO, where D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 WRITE WCLK 1 (1) t SKEW1 WEN RCLK ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 36-BIT FIFO COMMERCIAL AND INDUSTRIAL 28 TEMPERATURE RANGES APRIL 6, 2006 ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 36-BIT FIFO COMMERCIAL AND INDUSTRIAL 29 TEMPERATURE RANGES APRIL 6, 2006 ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690. ...
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... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690. ...
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... DS SI BIT 0 NOTE for the IDT72V3640 for the IDT72V3650 for the IDT72V3660 for the IDT72V3670 for the IDT72V3680 and for the IDT72V3690. Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) TM 36-BIT FIFO ...
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... In IDT Standard mode 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690. In FWFT mode 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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... In IDT Standard Mode 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690. In FWFT Mode 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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... In IDT Standard mode maximum FIFO depth 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690 FWFT mode maximum FIFO depth 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 RCLK REN FFA NOTE: ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 Write WCLK 1 WEN SKEW t CYL ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 CYC t t CYH CYL Last ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the ...
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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V3640 can easily be adapted to applications requiring depths greater than 1,024, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690 with an 36-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
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... RST (reset recovery) RSR Figure 31. Standard JTAG Timing JTAG AC ELECTRICAL CHARACTERISTICS (V = 3.3V CC Parameter IDT72V3640 IDT72V3650 IDT72V3660 JTAG Clock Input Period t IDT72V3670 JTAG Clock HIGH IDT72V3680 IDT72V3690 JTAG Clock Low Min. Max. Units JTAG Clock Rise Time - 20 ns ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support ...
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 ...
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... TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690, the Part Number field contains the following values: Device Part# Field IDT72V3640 IDT72V3650 IDT72V3660 IDT72V3670 IDT72V3680 IDT72V3690 TM 36-BIT FIFO 31(MSB) ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 7-5ns and 15ns are available as standard device. All other speed grades are available by special order. 2. Green parts are available. For ...