ISL12027 Intersil Corporation, ISL12027 Datasheet
ISL12027
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ISL12027 Summary of contents
Page 1
... Data Sheet Real Time Clock/Calendar with EEPROM The ISL12027 device is a low power real time clock with timing and crystal compensation, clock/calender, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, CPU Supervisor and integrated 512 x 8 bit EEPROM Byte per page format. ...
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... ISL12027IBAZ 12027IBAZ ISL12027IV27Z 2027I27Z ISL12027IV27AZ 202727AZ ISL12027IV30AZ 202730AZ ISL12027IVZ 2027IVZ ISL12027IVAZ 2027IVAZ NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Add “ ...
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... This input provides a backup supply voltage to the device. V BAT that the Power Supply ISL12027 BRIEF DESCRIPTION supply fails. This pin should be tied to ground if not used. DD threshold open drain active LOW TRIP supplies power to the device in the event BAT FN8232.3 ...
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... V Negative Slew rate DD SR- DD RESET OUTPUT V Output Low Voltage OL I Output Leakage Current LO 4 ISL12027 Thermal Information Thermal Resistance (Note SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering, 10s 300°C = +2.7V to +5.5V 3.3V DD CONDITIONS CONDITIONS ...
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... Minimum V for Valid RESET RVALID DD Output V ISL12027-4.5A Reset Voltage Level RESET ISL12027 Reset Voltage Level ISL12027-3 Reset Voltage Level ISL12027-2.7A Reset Voltage Level ISL12027-2.7 Reset Voltage Level t Watchdog Timer Period WDO t Watchdog Timer Reset Time-Out RST Delay Interface Minimum Restart Time ...
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... Write by the user the time from valid STOP condition at the end of Write WC sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 6 ISL12027 (Continued) CONDITIONS SCL rising edge to SDA falling edge. ...
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... BIT OF LAST BYTE t RSP SCL SDA RESET START Note: All inputs are ignored during the active reset period (t V RESET PURST t R RESET 7 ISL12027 HIGH LOW t SU:DAT t HD:DAT FIGURE 1. BUS TIMING ACK STOP CONDITION FIGURE 2. WRITE CYCLE TIMING t RSP t > ...
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... V BAT BAT, 5.00 4.50 Vdd=5.5V 4.00 3.50 Vdd=3.3V 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -45 -35 -25 - Temperature FIGURE TEMPERATURE DD3 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 1.8 2.3 2.8 3.3 3.8 Vdd (V) FIGURE DD3 8 ISL12027 Temperature is 25°C unless otherwise specified 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 4.3 4.8 5.3 SBIB = 0 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0. -20 -40 4.3 4.8 5.3 -32 -28 -24 -20 -16 -12 DD SCL,SDA pullups = 0V BSW = 1.80 2.30 2.80 3.30 3 ...
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... X1, X2 The X1 and X2 pins are the input and output, respectively inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12027 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can ...
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... The defined addresses are described in the Table 2. Writing to and reading from the undefined addresses are not recommended. 10 ISL12027 CCR Access The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a three step process (See section “ ...
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... RTCF: Real Time Clock Fail Bit This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL12027 internally) when the device powers up after having lost all power to the device 2 1 ...
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... RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be 12 ISL12027 according to the product variation, see device ordering information) BIT 6 5 ...
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... The effective on-chip series load capacitance, C ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default changed via two digitally LOAD controlled capacitors, C and C , connected from the ISL12027 and X2 pins to ground (see Figure 12). The value given by the following formula ⋅ ...
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... LVR Operation” in the Applications section for important details. VTS2, VTS1, VTS0: V Select Bits RESET The ISL12027 is shipped with a default per the ordering information table. This register is RESET a non-volatile with no protection, therefore any writes to this location can change the default value from that marked on the package ...
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... BATHYS • Condition 2: V < TRIP ≈ 2.2V where V TRIP • Battery Backup Mode ( Normal Mode (V BAT The ISL12027 device will switch from the V when one of the following conditions occurs: • Condition 1: V > BAT BATHYS ≈ 50mV where V BATHYS • ...
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... Power On Reset Application of power to the ISL12027 activates a Power On Reset Circuit that pulls the RESET pin active. This signal provides several benefits prevents the system microprocessor from starting to operate with insufficient voltage prevents the processor from operating prior to stabilization of the oscillator allows time for an FPGA to download its configuration prior to initialization of the circuit ...
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... When this R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 19. After loading the entire Slave Address Byte from the SDA bus, the ISL12027 compares the device identifier and device select bits with ‘1010111’ or ‘1101111’. Upon a correct 17 ISL12027 ...
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... ISL12027 will not initiate an internal write cycle, and will continue to ACK commands. Page Write The ISL12027 has a page write operation initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is ...
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... To do this, the master issues a start condition followed by the Memory Array Slave Address Byte for a write or read operation (AEh or AFh). If the ISL12027 is still busy with the non-volatile write cycle, then no ACK will be returned. When the ISL12027 has completed the write operation, an ACK is returned and the host can proceed with the read or write operation ...
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... In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 25. The ISL12027 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter ...
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... It is possible to address this variable drift by adjusting the load capacitance of the crystal, which will result in predictable change to the crystal frequency. The Intersil RTC family allows this adjustment over temperature since 21 ISL12027 SLAVE WORD WORD ADDRESS 0 ADDRESS 1 ...
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... These signals can couple into the oscillator circuit and produce double clocking or mis- clocking, seriously affecting the accuracy of the RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Figure 27 shows a suggested layout for the ISL12027 or ISL12026 devices. 22 ISL12027 MIN TYP ...
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... Standard mode and backup time is reduced. During initial power-up, the default mode is the Legacy mode. 23 ISL12027 2.7-5.5V FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT Communications During Battery Backup and ...
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... Mode this mode the selection bits indicate a low V switchover combined with no communications (3.0V) BAT (2.63V) RESET V TRIP (2.2V) RESET I BAT FIGURE 29. EXAMPLE RESET OPERATION IN MODE ISL12027 ACTIVE IN EE PROM WRITE/ BATTERY READ IN BATTERY BACKUP? BACKUP YES, only if YES V >V BAT BAT RESET NO NO ...
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... After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the AL0 bit in the status register to “1”. 25 ISL12027 tPURST Bus Active FIGURE 30. RESET OPERATION IN MODE D Example 2 – ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 26 ISL12027 M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 ISL12027 M8.173 8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE M ...