ISL6595 Intersil Corporation, ISL6595 Datasheet
ISL6595
Related parts for ISL6595
ISL6595 Summary of contents
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... Interleaved timing of the channels results in a higher ripple frequency, reducing input and output ripple. With up to six phases, each capable 2MHz operation, the ISL6595 can be used to build DC/DC converters that provide up to 200A with excellent efficiency, low ripple, and the lowest component count. ...
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... Pinout 48 1 VID7 VID6 2 VID5 3 VID4 4 VID3 5 VID2 6 VID1 7 VID0 8 VID_SEL 9 LL1 10 OUTEN 11 VDD ISL6595 ISL6595 (QFN) TOP VIEW EXPOSED PAD GND VDD 35 ISEN2+ ISEN2 PWM3 ISEN3+ 32 ISEN3- 31 PWM4 ...
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... OUTEN VID7 VID6 VID5 VID4 VID3 VID2 Deglitch VID1 VID0 VID_SEL LL1 LL0 FIGURE 1. BLOCK DIAGRAM FOR DIFFERENTIAL I-SENSE, PWM-ONLY OUTPUT 3 ISL6595 Window Comparator (OVP/UVP) Voltage ADC Current Balance Current ADC Channel Current AVP Internal Memory Digital Calibration Controller State Machine ...
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... ISEN4+ OUTEN ISEN4- PWM5 To µP VR_READY ISEN5+ ISEN5- Fault FAULT1 PWM6 Outputs FAULT2 ISEN6+ ISEN6- SDA TEMP_SEN I2C I/F SCL CAL_CUR_EN SADDR CAL_CUR_SEN VSENP VSENN 4 ISL6595 ` ISL6594A 1 UGATE PHASE 8 2 BOOT PVCC 7 3 PWM VCC GND LGATE 4.7µF ` ISL6594A UGATE PHASE 1 ...
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... Input LOW Voltage Input HIGH Voltage Input Current, Input Voltage Low Input Current, Input Voltage High Output LOW Voltage 5 ISL6595 Thermal Information Thermal Resistance (Typical, Note 1) QFN Package Maximum Junction Temperature (Plastic Package 0°C to 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s 300° ...
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... Voltage Threshold (Turn On) Voltage Threshold (Turn Off) SADDR INPUT Input LOW Voltage Input HIGH Voltage Input Current, Input Voltage LOW Input Current, Input Voltage HIGH Tri-State Input Bias Voltage 6 ISL6595 = +25°C, unless otherwise specified (Continued) C SYMBOL TEST CONDITIONS VSENP = 1.6V VSENN = 25°C ...
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... VIH(max) is guaranteed but not tested. Input current is typically less than 2mA at VIH = +4V. In applications requiring +5.5V tolerance, the device must be driven by a source impedance greater than 1kΩ. 5. Guaranteed but not tested in production. 6. Setting is programmable. 7. Guaranteed by calibration during production test. 7 ISL6595 = +25°C, unless otherwise specified (Continued) C SYMBOL TEST CONDITIONS V ...
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... I Analog 33 PWM3 O 3.3V CMOS 8 ISL6595 TYPE Bit 7 of processor voltage identification word (MSB of 8-bit VID word). Bit 6 of processor voltage identification word. Bit 5 of processor voltage identification word. Bit 4 of processor voltage identification word. Bit 3 of processor voltage identification word. Bit 2 of processor voltage identification word. ...
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... DS(on) Processor load line select input control signal (LSB). Selects regulator load line resistance and loadline offset voltage. Active LOW asynchronous system reset to place ISL6595 into default state. “1” asynchronous reset disabled “0” ...
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... FET. Soft-Start and Calibration Prior to entering an active regulating state, the ISL6595 performs a well-controlled, monotonic initial ramp or “soft- start”. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0 to the voltage set ...
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... The corner frequency can be lowered by adding series resistors in the board. Current Sensing and Current ADC The ISL6595 provides for precise current monitoring in each power stage, allowing for industry-leading loadline accuracy for active voltage positioning (AVP). The current in each power stage is sensed through one of three methods supported by the ISL6595 ...
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... ISEN6-) should be tied to the ground plane local to the low side FET being sensed to eliminate the effects of ground differences between the FET and the ISL6595. The large voltage swing at the drain of the low side FET is eliminated by using a series resistor, converting the signal to a current equal to: Isense = (Voffset – ...
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... Q + ph The target voltage is provided by external parallel 8-bit voltage identification (VID) inputs. The ISL6595 is fully compliant with VRD/VRM 11.0 deglitching and dynamic VID stepping requirements. VOLTAGE VID (HEX) VID (HEX 1.33125 5 7 1.325 ...
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... E 1.36875 5 1 1.3625 5 0 1.35625 1.34375 5 5 1.3375 NOTE: 8. VID = (VID4, VID3, VID2), VID = (VID1, VID0, VID5, VID6.25 ISL6595 VOLTAGE VID (HEX) VID (HEX) ( 1.24375 6 5 1.2375 6 4 1.23125 6 7 1.225 6 6 1.21875 6 9 1.2125 ...
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... ISL6595 TABLE 2. Intel® VR10 VID TABLE (8-BIT, Note 9) (Continued) VID VOLTAGE VID LO HI (HEX) (V) (HEX) 0 1.31250 2 1 1.30625 2 2 1.30000 2 3 1.29375 2 4 1.28750 2 5 1.28125 ...
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... The ISL6595 allows the user to independently force an offset A 0.15000 current to each channel, creating a current gradient. This causes the current balance to force the channels with B 0.14375 ...
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... Output Firing Sequence The PWM output and current sense (ISEN) pins of the ISL6595 have been assigned such that they can be placed sequentially for PC board layouts (i.e. phase 2 next to 1, phase 3 next to 2, etc...). The output phases are set in a pre-wired firing order to facilitate layout of high phase count systems ...
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... I C bus is 1110_000 or 1110_001, with the LSB set by the input pin SADDR. To write a register in the ISL6595, the master sends a control byte with the R/W bit set to 0, indicating a write receives an Acknowledge from the ISL6595 it sends a byte representing the address MSB. The ISL6595 will respond with an Acknowledge ...
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... I write, flash page erase) but the operation has not completed before the last Acknowledge slot in the I ISL6595 will add wait states by stretching the low portion of the last clock cycle. This also occurs in response to read/write requests to addresses that do not support physical memory in the ISL6595 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 ISL6595 TABLE 4. KEY REGISTERS (Continued) DESCRIPTION FORMAT ...
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Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L48.7x7P ...