ISL6722A INTERSIL [Intersil Corporation], ISL6722A Datasheet
ISL6722A
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ISL6722A Summary of contents
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... Boost Regulators LGND SS Ordering Information COMP PART FB NUMBER* (Note) ISL6722AABZ 6722AABZ -40 to +105 16 Ld SOIC ISL6723AABZ 6723AABZ -40 to +105 16 Ld SOIC ISL6722AAVZ 6722AAVZ ISL6722AARZ 22AZ 12 VCC *Add “-T” suffix to part number for tape and reel packaging. 11 VREF NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets ...
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... Functional Block Diagram (ISL6722A START/STOP UV COMPARATOR + ENABLE - + - BG LGND RESTART SLEEP DELAY ISET 0.8 ISENSE VREF S + 53µA OVERCURRENT + 100mV COMPARATOR SLOPE 0 CLAMP + COMP - ERROR AMPLIFIER 2. VFB VREF 20k 3.0V/ 12k 1.5V ON 30k OSCILLATOR COMPARATOR - + 1mA ON 2 ISL6722A, ISL6723A V REF 5V SS CHARGE VOLTAGE CLAMP ...
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... VFB VREF 20k 3.0V/ 12k 1.5V ON 30k OSCILLATOR COMPARATOR - + RTCT 1mA VREF 100 SYNC 4.5k 3 ISL6722A, ISL6723A VREF CHARGE VOLTAGE CLAMP SS CHARGED OC DETECT SHTDN COMPARATOR PWM COMPARATOR + - UV COMPARATOR START 1/3 100nS BLANKING S Q BI-DIRECTIONAL SYNCHRONIZATION R Q OSC IN CLK OUT NO EXT SYNC EXT SYNC BLANKING ...
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Typical Application - 48V Input Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A P9 VIN+ R1 36V TO 75V C1 R2 VIN- SLEEP VR1 ISOLATION C18 R24 C2 CR2 C5 CR6 C3 TP1 ...
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... Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A Operating Conditions Temperature Range ISL6722AAxZ . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C ISL6723AAxZ . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Supply Voltage Range (Typical 9VDC to 18VDC CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty ...
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... Comparator High Threshold w/Ext. SYNC (ISL6723A) (Note 6) Comparator Low Threshold Discharge Current SOFT-START Charging Current Charged Threshold Voltage Initial Overcurrent Discharge Current Overcurrent Shutdown Threshold Voltage Fault Discharge Current Reset Threshold Voltage 6 ISL6722A, ISL6723A = V < 20V 11kΩ 330pF +25°C (Continued) A TEST CONDITIONS (Note 0V ...
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... Undervoltage Fault Threshold Undervoltage Clear Threshold Undervoltage Hysteresis Voltage UV Bias Current OV Bias Current SLEEP (ISL6722A) SLEEP Input Threshold Voltage SLEEP Input Current I @ SLEEP CC 7 ISL6722A, ISL6723A = V < 20V 11kΩ 330pF +25°C (Continued) A TEST CONDITIONS SLOPE = 2V +105° -40° ...
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... TEMPERATURE (°C) FIGURE 1. EA REFERENCE VOLTAGE vs TEMPERATURE 1.002 0.996 0.989 0.983 0.976 0.970 -40 -10 20 TEMPERATURE (°C) FIGURE 3. OSCILLATOR FREQUENCY vs TEMPERATURE 8 ISL6722A, ISL6723A = V < 20V 11kΩ 330pF +25°C (Continued) A TEST CONDITIONS (Note 4.5kΩ LOAD R = open LOAD SYNC rising edge to GATE falling ...
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... GND during each switching cycle. The resulting ramp is scaled and added to the ISENSE signal. SLEEP (ISL6722A logic level control input that disables the IC and activates the low power standby mode. SLEEP is active high. SYNC (ISL6723A bidirectional synchronization signal used to coordinate the switching frequency of multiple units ...
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... SYNC signal terminates the cycle), the oscillator reverts to the internal clock mode and a SYNC signal is generated. Soft-Start Operation The ISL6722A and ISL6723A feature a soft-start using an external capacitor in conjunction with an internal current source. Soft-start is used to reduce voltage stresses and surge currents during start up. ...
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... A more rigorous treatment of slope compensation can be obtained from the small signal current-mode model [1]. It can 11 ISL6722A, ISL6723A be shown that the naturally-sampled modulator gain, Fm, without slope compensation, is Equation 9: 1 -------------------- - ...
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... Adding slope compensation is accomplished in the ISL6722A, ISL6723A using the SLOPE input. The value of Ve determined in Equation 16, multiplied 10x, is the voltage required at the SLOPE input. ⋅ SLOPE ON ---------------------------------- - C = ⋅ SLOPE V 10 ...
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... PGND with good high frequency capacitors. The return connection for input power and the bulk input capacitor should be connected to the PGND ground plane. Reference Design The Typical Application Schematic features the ISL6722A in 295ms a conventional dual output 10W discontinuous mode flyback DC/DC converter. The ISL6722AEVAL1 demonstration unit implements this design and is available for evaluation ...
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... Determine the number of primary turns. • Determine the turns ratio. • Select the wire gauge for each winding. • Determine winding order and insulation requirements. • Verify the design. 14 ISL6722A, ISL6723A Input Power: P /Efficiency = 14.3W (use 15W) OUT Max On Time: t ON(max) Average Input Current: Iavg(in) = Pin/Vin(min ...
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... Ip rms = Ippk ------------------------ - A • ISL6722A, ISL6723A The peak and RMS current values in the remaining windings may be calculated in Equation 28: Ispk = Irms = The RMS current for the primary winding is 0.72A, for the 3.3V output, 4.23A, for the 1.8V output, 1.69A, and for the bias winding, 85mA. ...
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... This estimate may predict higher dissipation than is realized because a portion of the turn off drain current is attributable to the charging of the device output capacitance (Coss) and is not dissipative during this portion of the switching cycle. 16 ISL6722A, ISL6723A (EQ. 30 DS(ON) ...
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... Control Loop Design The major components of the feedback control loop are a programmable shunt regulator, an opto-coupler, and the inverting amplifier of the ISL6722A. The opto-coupler is used to transfer the error signal across the isolation barrier. The opto-coupler offers a convenient means to cross the isolation barrier, but it adds complexity to the feedback control loop ...
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... PWM comparator. The Type 2 compensation configuration has two poles and one zero. The first pole is at the origin, and provides the 18 ISL6722A, ISL6723A integration characteristic which results in excellent DC regulation. Referring to the “Typical Application - 48V Input Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A” on page 4, ...
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... A Bode plot of the closed loop system at low line, max load appears below -10 -20 -30 -40 -50 0.01 0.1 1 FREQUENCY (kHz) FIGURE 12A. GAIN 200 150 100 100 0.01 0.1 1 FREQUENCY (kHz) FIGURE 12B. PHASE MARGIN 19 ISL6722A, ISL6723A Regulation Performance TABLE 1. OUTPUT LOAD REGULATION (A), 3.3V OUT 0 0.39 0.88 1.38 1.87 2.39 2.89 10 100 3.37 0 0.39 0.88 1.38 1.87 2.39 2.89 0 0.39 0.88 1.38 1.87 2.39 10 100 0 0 ...
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... Typical waveforms can be found in Figures 13 through 15. These waveforms are taken from an ISL6721EVAL1 evaluation board, and therefore include synchronization waveforms that are not applicable to the ISL6722A, but are otherwise representative. Figure 13 shows the steady state operation of the sawtooth oscillator waveform at RTCT (Trace 2), the SYNC output pulse (Trace 1), and the GATE output to the converter FET (Trace 3) ...
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... Resistor, 2512, 1% Resistor, 0603, 1% Resistor, 0603, 1% OMIT Transformer, MIDCOM 31555 Opto-coupler, NEC PS2801-1 Shunt Reference, National LM431BIM3 PWM, Intersil ISL6722AABZ Zener, 15V, Zetex BZX84C15 [2] Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode Power Supply Design Seminar, SEM-700, 1990. DESCRIPTION July 11, 2007 FN9237.1 ...
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... Package Outline Drawing L16.3x3B 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 2. 80 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 22 ISL6722A, ISL6723A ± 0.1 ( 12X 16X 16X 0 . 60) NOTES: 1. Dimensions are in millimeters. Dimensions ...
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... Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. (Angles in degrees) 23 ISL6722A, ISL6723A M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 ISL6722A, ISL6723A M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE ...